include/configs/CPC45.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  *
  10  * Configuration settings for the CPC45 board.
  11  *
  12  */
  13
  14 /* ------------------------------------------------------------------------- */
  15
  16 /*
  17  * board/config.h - configuration options, board specific
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  * (easy to change)
  26  */
  27
  28 #define CONFIG_MPC824X          1
  29 #define CONFIG_MPC8245          1
  30 #define CONFIG_CPC45            1
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  33
  34 #define CONFIG_CONS_INDEX       1
  35 #define CONFIG_BAUDRATE         9600
  36
  37 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  38
  39 #define CONFIG_BOOTDELAY        5
  40
  41 /*
  42  * BOOTP options
  43  */
  44 #define CONFIG_BOOTP_SUBNETMASK
  45 #define CONFIG_BOOTP_GATEWAY
  46 #define CONFIG_BOOTP_HOSTNAME
  47 #define CONFIG_BOOTP_BOOTPATH
  48
  49 #define CONFIG_BOOTP_BOOTFILESIZE
  50
  51
  52 /*
  53  * Command line configuration.
  54  */
  55 #include <config_cmd_default.h>
  56
  57 #define CONFIG_CMD_BEDBUG
  58 #define CONFIG_CMD_DATE
  59 #define CONFIG_CMD_DHCP
  60 #define CONFIG_CMD_EEPROM
  61 #define CONFIG_CMD_EXT2
  62 #define CONFIG_CMD_FAT
  63 #define CONFIG_CMD_FLASH
  64 #define CONFIG_CMD_I2C
  65 #define CONFIG_CMD_IDE
  66 #define CONFIG_CMD_NFS
  67 #define CONFIG_CMD_PCI
  68 #define CONFIG_CMD_PING
  69 #define CONFIG_CMD_SDRAM
  70 #define CONFIG_CMD_SNTP
  71
  72
  73 /*
  74  * Miscellaneous configurable options
  75  */
  76 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  77 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  78 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  79
  80 #if 1
  81 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
  82 #endif
  83
  84 /* Print Buffer Size
  85  */
  86 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  87
  88 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  89 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  90 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
  91
  92 /*-----------------------------------------------------------------------
  93  * Start addresses for the final memory configuration
  94  * (Set up by the startup code)
  95  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  96  */
  97
  98 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  99
 100 #if defined(CONFIG_BOOT_ROM)
 101 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 102 #else
 103 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 104 #endif
 105
 106 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 107
 108 #define CONFIG_SYS_EUMB_ADDR            0xFCE00000
 109
 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 111
 112 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 113 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 114
 115 #define CONFIG_SYS_MEMTEST_START        0x00004000      /* memtest works on             */
 116 #define CONFIG_SYS_MEMTEST_END          0x02000000      /* 0 ... 32 MB in DRAM          */
 117
 118 /* Maximum amount of RAM.
 119  */
 120 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
 121
 122
 123 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 124 #undef CONFIG_SYS_RAMBOOT
 125 #else
 126 #define CONFIG_SYS_RAMBOOT
 127 #endif
 128
 129
 130 /*-----------------------------------------------------------------------
 131  * Definitions for initial stack pointer and data area
 132  */
 133
 134 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 135 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 136 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 137
 138 /*
 139  * NS16550 Configuration
 140  */
 141 #define CONFIG_SYS_NS16550
 142 #define CONFIG_SYS_NS16550_SERIAL
 143
 144 #define CONFIG_SYS_NS16550_REG_SIZE     1
 145
 146 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 147
 148 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 149 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 150 #define DUART_DCR               (CONFIG_SYS_EUMB_ADDR + 0x4511)
 151
 152 /*
 153  * I2C configuration
 154  */
 155 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 156
 157 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 158 #define CONFIG_SYS_I2C_SLAVE            0x7F
 159
 160 /*
 161  * RTC configuration
 162  */
 163 #define CONFIG_RTC_PCF8563
 164 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 165
 166 /*
 167  * EEPROM configuration
 168  */
 169 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 170 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 171 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 174
 175 /*
 176  * Low Level Configuration Settings
 177  * (address mappings, register initial values, etc.)
 178  * You should know what you are doing if you make changes here.
 179  * For the detail description refer to the MPC8240 user's manual.
 180  */
 181
 182 #define CONFIG_SYS_CLK_FREQ     33000000
 183 #define CONFIG_SYS_HZ                   1000
 184
 185
 186 /* Bit-field values for MCCR1.
 187  */
 188 #define CONFIG_SYS_ROMNAL               0
 189 #define CONFIG_SYS_ROMFAL               8
 190
 191 #define CONFIG_SYS_BANK0_ROW            0       /* SDRAM bank 7-0 row address */
 192 #define CONFIG_SYS_BANK1_ROW            0
 193 #define CONFIG_SYS_BANK2_ROW            0
 194 #define CONFIG_SYS_BANK3_ROW            0
 195 #define CONFIG_SYS_BANK4_ROW            0
 196 #define CONFIG_SYS_BANK5_ROW            0
 197 #define CONFIG_SYS_BANK6_ROW            0
 198 #define CONFIG_SYS_BANK7_ROW            0
 199
 200 /* Bit-field values for MCCR2.
 201  */
 202
 203 #define CONFIG_SYS_REFINT               0x2ec
 204
 205 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 206  */
 207 #define CONFIG_SYS_BSTOPRE              160
 208
 209 /* Bit-field values for MCCR3.
 210  */
 211 #define CONFIG_SYS_REFREC               2       /* Refresh to activate interval         */
 212 #define CONFIG_SYS_RDLAT                0       /* Data latancy from read command       */
 213
 214 /* Bit-field values for MCCR4.
 215  */
 216 #define CONFIG_SYS_PRETOACT             2       /* Precharge to activate interval       */
 217 #define CONFIG_SYS_ACTTOPRE             5       /* Activate to Precharge interval       */
 218 #define CONFIG_SYS_SDMODE_CAS_LAT       2       /* SDMODE CAS latancy                   */
 219 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 220 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* SDMODE Burst length                  */
 221 #define CONFIG_SYS_ACTORW               2
 222 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 223 #define CONFIG_SYS_EXTROM               0
 224 #define CONFIG_SYS_REGDIMM              0
 225
 226 /* Memory bank settings.
 227  * Only bits 20-29 are actually used from these vales to set the
 228  * start/end addresses. The upper two bits will always be 0, and the lower
 229  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 230  * address. Refer to the MPC8240 book.
 231  */
 232
 233 #define CONFIG_SYS_BANK0_START          0x00000000
 234 #define CONFIG_SYS_BANK0_END            (CONFIG_SYS_MAX_RAM_SIZE - 1)
 235 #define CONFIG_SYS_BANK0_ENABLE 1
 236 #define CONFIG_SYS_BANK1_START          0x3ff00000
 237 #define CONFIG_SYS_BANK1_END            0x3fffffff
 238 #define CONFIG_SYS_BANK1_ENABLE 0
 239 #define CONFIG_SYS_BANK2_START          0x3ff00000
 240 #define CONFIG_SYS_BANK2_END            0x3fffffff
 241 #define CONFIG_SYS_BANK2_ENABLE 0
 242 #define CONFIG_SYS_BANK3_START          0x3ff00000
 243 #define CONFIG_SYS_BANK3_END            0x3fffffff
 244 #define CONFIG_SYS_BANK3_ENABLE 0
 245 #define CONFIG_SYS_BANK4_START          0x3ff00000
 246 #define CONFIG_SYS_BANK4_END            0x3fffffff
 247 #define CONFIG_SYS_BANK4_ENABLE 0
 248 #define CONFIG_SYS_BANK5_START          0x3ff00000
 249 #define CONFIG_SYS_BANK5_END            0x3fffffff
 250 #define CONFIG_SYS_BANK5_ENABLE 0
 251 #define CONFIG_SYS_BANK6_START          0x3ff00000
 252 #define CONFIG_SYS_BANK6_END            0x3fffffff
 253 #define CONFIG_SYS_BANK6_ENABLE 0
 254 #define CONFIG_SYS_BANK7_START          0x3ff00000
 255 #define CONFIG_SYS_BANK7_END            0x3fffffff
 256 #define CONFIG_SYS_BANK7_ENABLE 0
 257
 258 #define CONFIG_SYS_ODCR         0xff
 259 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 260                                         /* currently accessed page in memory    */
 261                                         /* see 8240 book for details            */
 262
 263 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 264 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 265
 266 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 267 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 268
 269 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 270 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 271
 272 #define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 273 #define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
 274
 275 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 276 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 277 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 278 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 279 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 280 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 281 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 282 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 283
 284 /*
 285  * For booting Linux, the board info and command line data
 286  * have to be in the first 8 MB of memory, since this is
 287  * the maximum mapped by the Linux kernel during initialization.
 288  */
 289 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 290
 291 /*-----------------------------------------------------------------------
 292  * FLASH organization
 293  */
 294 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* Max number of flash banks            */
 295 #define CONFIG_SYS_MAX_FLASH_SECT       39      /* Max number of sectors in one bank    */
 296 #define INTEL_ID_28F160F3T      0x88F388F3      /*  16M = 1M x 16 top boot sector       */
 297 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 298 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 299
 300         /* Warining: environment is not EMBEDDED in the ppcboot code.
 301          * It's stored in flash separately.
 302          */
 303 #define CONFIG_ENV_IS_IN_FLASH      1
 304
 305 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x7F8000)
 306 #define CONFIG_ENV_SIZE         0x4000  /* Size of the Environment              */
 307 #define CONFIG_ENV_OFFSET               0       /* starting right at the beginning      */
 308 #define CONFIG_ENV_SECT_SIZE    0x8000 /* Size of the Environment Sector        */
 309
 310 /*-----------------------------------------------------------------------
 311  * Cache Configuration
 312  */
 313 #define CONFIG_SYS_CACHELINE_SIZE       32
 314 #if defined(CONFIG_CMD_KGDB)
 315 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 316 #endif
 317
 318 /*----------------------------------------------------------------------*/
 319 /* CPC45 Memory Map                                                     */
 320 /*----------------------------------------------------------------------*/
 321 #define SRAM_BASE       0x80000000      /* SRAM base address            */
 322 #define SRAM_END        0x801FFFFF
 323 #define ST16552_A_BASE  0x80200000      /* ST16552 channel A            */
 324 #define ST16552_B_BASE  0x80400000      /* ST16552 channel A            */
 325 #define BCSR_BASE       0x80600000      /* board control / status registers */
 326 #define DISPLAY_BASE    0x80600040      /* DISPLAY base                 */
 327 #define PCMCIA_MEM_BASE 0x83000000      /* PCMCIA memory window base    */
 328 #define PCMCIA_IO_BASE  0xFE000000      /* PCMCIA IO window base        */
 329
 330 #define CONFIG_SYS_SRAM_BASE    SRAM_BASE
 331 #define CONFIG_SYS_SRAM_SIZE    (SRAM_END - SRAM_BASE + 1)
 332
 333 /*---------------------------------------------------------------------*/
 334 /* CPC45 Control/Status Registers                                      */
 335 /*---------------------------------------------------------------------*/
 336 #define IRQ_ENA_1               *((volatile uchar*)(BCSR_BASE + 0x00))
 337 #define IRQ_STAT_1              *((volatile uchar*)(BCSR_BASE + 0x01))
 338 #define IRQ_ENA_2               *((volatile uchar*)(BCSR_BASE + 0x02))
 339 #define IRQ_STAT_2              *((volatile uchar*)(BCSR_BASE + 0x03))
 340 #define BOARD_CTRL              *((volatile uchar*)(BCSR_BASE + 0x04))
 341 #define BOARD_STAT              *((volatile uchar*)(BCSR_BASE + 0x05))
 342 #define WDG_START               *((volatile uchar*)(BCSR_BASE + 0x06))
 343 #define WDG_PRESTOP             *((volatile uchar*)(BCSR_BASE + 0x06))
 344 #define WDG_STOP                *((volatile uchar*)(BCSR_BASE + 0x06))
 345 #define BOARD_REV               *((volatile uchar*)(BCSR_BASE + 0x07))
 346
 347 /* IRQ_ENA_1 bit definitions */
 348 #define I_ENA_1_IERA    0x80            /* INTA enable                  */
 349 #define I_ENA_1_IERB    0x40            /* INTB enable                  */
 350 #define I_ENA_1_IERC    0x20            /* INTC enable                  */
 351 #define I_ENA_1_IERD    0x10            /* INTD enable                  */
 352
 353 /* IRQ_STAT_1 bit definitions */
 354 #define I_STAT_1_INTA   0x80            /* INTA status                  */
 355 #define I_STAT_1_INTB   0x40            /* INTB status                  */
 356 #define I_STAT_1_INTC   0x20            /* INTC status                  */
 357 #define I_STAT_1_INTD   0x10            /* INTD status                  */
 358
 359 /* IRQ_ENA_2 bit definitions */
 360 #define I_ENA_2_IEAB    0x80            /* ABORT IRQ enable             */
 361 #define I_ENA_2_IEK1    0x40            /* KEY1 IRQ enable              */
 362 #define I_ENA_2_IEK2    0x20            /* KEY2 IRQ enable              */
 363 #define I_ENA_2_IERT    0x10            /* RTC IRQ enable               */
 364 #define I_ENA_2_IESM    0x08            /* LM81 IRQ enable              */
 365 #define I_ENA_2_IEDG    0x04            /* DEGENERATING IRQ enable      */
 366 #define I_ENA_2_IES2    0x02            /* ST16552/B IRQ enable         */
 367 #define I_ENA_2_IES1    0x01            /* ST16552/A IRQ enable         */
 368
 369 /* IRQ_STAT_2 bit definitions */
 370 #define I_STAT_2_ABO    0x80            /* ABORT IRQ status             */
 371 #define I_STAT_2_KY1    0x40            /* KEY1 IRQ status              */
 372 #define I_STAT_2_KY2    0x20            /* KEY2 IRQ status              */
 373 #define I_STAT_2_RTC    0x10            /* RTC IRQ status               */
 374 #define I_STAT_2_SMN    0x08            /* LM81 IRQ status              */
 375 #define I_STAT_2_DEG    0x04            /* DEGENERATING IRQ status      */
 376 #define I_STAT_2_SIO2   0x02            /* ST16552/B IRQ status         */
 377 #define I_STAT_2_SIO1   0x01            /* ST16552/A IRQ status         */
 378
 379 /* BOARD_CTRL bit definitions */
 380 #define USER_LEDS               2                       /* 2 user LEDs  */
 381
 382 #if (USER_LEDS == 4)
 383 #define B_CTRL_WRSE             0x80
 384 #define B_CTRL_KRSE             0x40
 385 #define B_CTRL_FWRE             0x20            /* Flash write enable           */
 386 #define B_CTRL_FWPT             0x10            /* Flash write protect          */
 387 #define B_CTRL_LED3             0x08            /* LED 3 control                */
 388 #define B_CTRL_LED2             0x04            /* LED 2 control                */
 389 #define B_CTRL_LED1             0x02            /* LED 1 control                */
 390 #define B_CTRL_LED0             0x01            /* LED 0 control                */
 391 #else
 392 #define B_CTRL_WRSE             0x80
 393 #define B_CTRL_KRSE             0x40
 394 #define B_CTRL_FWRE_1           0x20            /* Flash write enable           */
 395 #define B_CTRL_FWPT_1           0x10            /* Flash write protect          */
 396 #define B_CTRL_LED1             0x08            /* LED 1 control                */
 397 #define B_CTRL_LED0             0x04            /* LED 0 control                */
 398 #define B_CTRL_FWRE_0           0x02            /* Flash write enable           */
 399 #define B_CTRL_FWPT_0           0x01            /* Flash write protect          */
 400 #endif
 401
 402 /* BOARD_STAT bit definitions */
 403 #define B_STAT_WDGE             0x80
 404 #define B_STAT_WDGS             0x40
 405 #define B_STAT_WRST             0x20
 406 #define B_STAT_KRST             0x10
 407 #define B_STAT_CSW3             0x08            /* sitch bit 3 status           */
 408 #define B_STAT_CSW2             0x04            /* sitch bit 2 status           */
 409 #define B_STAT_CSW1             0x02            /* sitch bit 1 status           */
 410 #define B_STAT_CSW0             0x01            /* sitch bit 0 status           */
 411
 412 /*---------------------------------------------------------------------*/
 413 /* Display addresses                                                   */
 414 /*---------------------------------------------------------------------*/
 415 #define DISP_UDC_RAM    (DISPLAY_BASE + 0x08)   /* UDC RAM             */
 416 #define DISP_CHR_RAM    (DISPLAY_BASE + 0x18)   /* character Ram       */
 417 #define DISP_FLASH      (DISPLAY_BASE + 0x20)   /* Flash Ram           */
 418
 419 #define DISP_UDC_ADR    *((volatile uchar*)(DISPLAY_BASE + 0x00))       /* UDC Address Reg.    */
 420 #define DISP_CWORD      *((volatile uchar*)(DISPLAY_BASE + 0x10))       /* Control Word Reg.   */
 421
 422 #define DISP_DIG0       *((volatile uchar*)(DISP_CHR_RAM + 0x00))       /* Digit 0 address     */
 423 #define DISP_DIG1       *((volatile uchar*)(DISP_CHR_RAM + 0x01))       /* Digit 0 address     */
 424 #define DISP_DIG2       *((volatile uchar*)(DISP_CHR_RAM + 0x02))       /* Digit 0 address     */
 425 #define DISP_DIG3       *((volatile uchar*)(DISP_CHR_RAM + 0x03))       /* Digit 0 address     */
 426 #define DISP_DIG4       *((volatile uchar*)(DISP_CHR_RAM + 0x04))       /* Digit 0 address     */
 427 #define DISP_DIG5       *((volatile uchar*)(DISP_CHR_RAM + 0x05))       /* Digit 0 address     */
 428 #define DISP_DIG6       *((volatile uchar*)(DISP_CHR_RAM + 0x06))       /* Digit 0 address     */
 429 #define DISP_DIG7       *((volatile uchar*)(DISP_CHR_RAM + 0x07))       /* Digit 0 address     */
 430
 431
 432 /*-----------------------------------------------------------------------
 433  * PCI stuff
 434  *-----------------------------------------------------------------------
 435  */
 436 #define CONFIG_PCI                      /* include pci support                  */
 437 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 438 #define CONFIG_SYS_EARLY_PCI_INIT
 439 #undef  CONFIG_PCI_PNP
 440 #undef  CONFIG_PCI_SCAN_SHOW
 441
 442
 443 #define CONFIG_EEPRO100
 444 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 445
 446 #define PCI_ENET0_IOADDR        0x82000000
 447 #define PCI_ENET0_MEMADDR       0x82000000
 448 #define PCI_PLX9030_IOADDR      0x82100000
 449 #define PCI_PLX9030_MEMADDR     0x82100000
 450
 451 /*-----------------------------------------------------------------------
 452  * PCMCIA stuff
 453  *-----------------------------------------------------------------------
 454  */
 455
 456 #define CONFIG_I82365
 457
 458 #define CONFIG_SYS_PCMCIA_MEM_ADDR      PCMCIA_MEM_BASE
 459 #define CONFIG_SYS_PCMCIA_MEM_SIZE      0x1000
 460
 461 #define CONFIG_PCMCIA_SLOT_A
 462
 463 /*-----------------------------------------------------------------------
 464  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 465  *-----------------------------------------------------------------------
 466  */
 467
 468 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 469 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 470
 471 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 472 #undef  CONFIG_IDE_RESET                /* reset for IDE not supported  */
 473 #define CONFIG_IDE_LED                  /* LED   for IDE is  supported  */
 474
 475 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 476 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 477
 478 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 479
 480 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 481
 482 #define CONFIG_SYS_ATA_DATA_OFFSET      CONFIG_SYS_PCMCIA_MEM_SIZE
 483
 484 /* Offset for normal register accesses  */
 485 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 486
 487 /* Offset for alternate registers       */
 488 #define CONFIG_SYS_ATA_ALT_OFFSET       (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
 489
 490 #define CONFIG_DOS_PARTITION
 491
 492 #endif  /* __CONFIG_H */