include/configs/CPCI405.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_CPCI405          1       /* ...on a CPCI405 board        */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  24
  25 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  26 #define CONFIG_MISC_INIT_R       1      /* call misc_init_r()           */
  27
  28 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  29
  30 #define CONFIG_BAUDRATE         9600
  31 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  32
  33 #undef  CONFIG_BOOTARGS
  34 #undef  CONFIG_BOOTCOMMAND
  35
  36 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  37
  38 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  39 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  40
  41 #define CONFIG_PPC4xx_EMAC
  42 #define CONFIG_MII              1       /* MII PHY management           */
  43 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  44 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  45 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  46
  47 #undef  CONFIG_HAS_ETH1
  48
  49 /*
  50  * BOOTP options
  51  */
  52 #define CONFIG_BOOTP_SUBNETMASK
  53 #define CONFIG_BOOTP_GATEWAY
  54 #define CONFIG_BOOTP_HOSTNAME
  55 #define CONFIG_BOOTP_BOOTPATH
  56 #define CONFIG_BOOTP_DNS
  57 #define CONFIG_BOOTP_DNS2
  58 #define CONFIG_BOOTP_SEND_HOSTNAME
  59
  60
  61 /*
  62  * Command line configuration.
  63  */
  64 #include <config_cmd_default.h>
  65
  66 #define CONFIG_CMD_DHCP
  67 #define CONFIG_CMD_PCI
  68 #define CONFIG_CMD_IRQ
  69 #define CONFIG_CMD_IDE
  70 #define CONFIG_CMD_FAT
  71 #define CONFIG_CMD_ELF
  72 #define CONFIG_CMD_MII
  73 #define CONFIG_CMD_EEPROM
  74
  75
  76 #define CONFIG_MAC_PARTITION
  77 #define CONFIG_DOS_PARTITION
  78
  79 #define CONFIG_SUPPORT_VFAT
  80
  81 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  82
  83 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  84
  85 /*
  86  * Miscellaneous configurable options
  87  */
  88 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  89
  90 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  91
  92 #if defined(CONFIG_CMD_KGDB)
  93 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  94 #else
  95 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  96 #endif
  97 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  98 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  99 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 100
 101 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 102
 103 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 104
 105 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 106 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 107
 108 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 109 #define CONFIG_SYS_NS16550
 110 #define CONFIG_SYS_NS16550_SERIAL
 111 #define CONFIG_SYS_NS16550_REG_SIZE     1
 112 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 113
 114 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 115 #define CONFIG_SYS_BASE_BAUD        691200
 116
 117 /* The following table includes the supported baudrates */
 118 #define CONFIG_SYS_BAUDRATE_TABLE       \
 119         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 120          57600, 115200, 230400, 460800, 921600 }
 121
 122 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 123 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 124
 125 #define CONFIG_LOOPW            1       /* enable loopw command         */
 126
 127 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 128
 129 /*-----------------------------------------------------------------------
 130  * PCI stuff
 131  *-----------------------------------------------------------------------
 132  */
 133 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 134 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 135 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 136
 137 #define CONFIG_PCI                      /* include pci support          */
 138 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 139 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 140 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 141                                         /* resource configuration       */
 142
 143 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 144
 145 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 146
 147 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 148
 149 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 150 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 151 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 152 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 153 #define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 154 #define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 155 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 156 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 157 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 158 #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
 159
 160 #define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 161
 162 /*-----------------------------------------------------------------------
 163  * IDE/ATA stuff
 164  *-----------------------------------------------------------------------
 165  */
 166 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 167 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 168 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 169
 170 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 171 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 172
 173 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 174 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 175
 176 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 177 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 178 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 179
 180 /*-----------------------------------------------------------------------
 181  * Start addresses for the final memory configuration
 182  * (Set up by the startup code)
 183  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 184  */
 185 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 186 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE
 187 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 188 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 189 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 190
 191 /*
 192  * For booting Linux, the board info and command line data
 193  * have to be in the first 8 MB of memory, since this is
 194  * the maximum mapped by the Linux kernel during initialization.
 195  */
 196 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 202
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 205
 206 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 207 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 208 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 209 /*
 210  * The following defines are added for buggy IOP480 byte interface.
 211  * All other boards should use the standard values (CPCI405 etc.)
 212  */
 213 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 214 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 215 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 216
 217 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 218
 219 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0200000              /* NVRAM base address   */
 220 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)               /* NVRAM size           */
 221 #define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 222
 223 #if 1 /* Use NVRAM for environment variables */
 224 /*-----------------------------------------------------------------------
 225  * NVRAM organization
 226  */
 227 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
 228 #define CONFIG_ENV_SIZE         0x1000          /* Size of Environment vars     */
 229 #define CONFIG_ENV_ADDR         \
 230         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)      /* Env  */
 231
 232 #else /* Use EEPROM for environment variables */
 233
 234 #define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 235 #define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 236 #define CONFIG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
 237                                    /* total size of a CAT24WC08 is 1024 bytes */
 238 #endif
 239
 240 /*-----------------------------------------------------------------------
 241  * I2C EEPROM (CAT24WC08) for environment
 242  */
 243 #define CONFIG_SYS_I2C
 244 #define CONFIG_SYS_I2C_PPC4XX
 245 #define CONFIG_SYS_I2C_PPC4XX_CH0
 246 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 247 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 248
 249 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 250 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 251 /* mask of address bits that overflow into the "EEPROM chip address"    */
 252 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 254                                         /* 16 byte page write mode using*/
 255                                         /* last 4 bits of the address   */
 256 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 257
 258 /*
 259  * Init Memory Controller:
 260  *
 261  * BR0/1 and OR0/1 (FLASH)
 262  */
 263
 264 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 265 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 266
 267 /*-----------------------------------------------------------------------
 268  * External Bus Controller (EBC) Setup
 269  */
 270
 271 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 272 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 273 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 274
 275 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 276 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 277 #define CONFIG_SYS_EBC_PB1CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 278
 279 /* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization                        */
 280 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 281 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 282
 283 /* Memory Bank 3 (CompactFlash IDE) initialization                              */
 284 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 285 #define CONFIG_SYS_EBC_PB3CR            0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 286
 287 /* Memory Bank 4 (NVRAM) initialization                                         */
 288 #define CONFIG_SYS_EBC_PB4AP            0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
 289 #define CONFIG_SYS_EBC_PB4CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 290
 291 /* Memory Bank 5 (Quart) initialization                                         */
 292 #define CONFIG_SYS_EBC_PB5AP            0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
 293 #define CONFIG_SYS_EBC_PB5CR            0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 294
 295 /*-----------------------------------------------------------------------
 296  * FPGA stuff
 297  */
 298
 299 /* FPGA program pin configuration */
 300 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 301 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 302 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 303 #define CONFIG_SYS_FPGA_INIT            0x00400000  /* FPGA init pin (ppc input)     */
 304 #define CONFIG_SYS_FPGA_DONE            0x00800000  /* FPGA done pin (ppc input)     */
 305
 306 /*-----------------------------------------------------------------------
 307  * Definitions for initial stack pointer and data area (in data cache)
 308  */
 309 #if 1 /* test-only */
 310 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 311
 312 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 313 #else
 314 #define CONFIG_SYS_INIT_RAM_ADDR        0x00df0000 /* inside of SDRAM                   */
 315 #endif
 316 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 317 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 318 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 319
 320 #endif  /* __CONFIG_H */