include/configs/CPCI750.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 /*************************************************************************
  29  * (c) 2004 esd gmbh Hannover
  30  *
  31  *
  32  * from db64360.h file
  33  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  34  *
  35   ************************************************************************/
  36
  37
  38 #ifndef __CONFIG_H
  39 #define __CONFIG_H
  40
  41 /* This define must be before the core.h include */
  42 #define CONFIG_CPCI750          1       /* this is an CPCI750 board     */
  43
  44 #ifndef __ASSEMBLY__
  45 #include <../board/Marvell/include/core.h>
  46 #endif
  47 /*-----------------------------------------------------*/
  48
  49 #include "../board/esd/cpci750/local.h"
  50
  51 /*
  52  * High Level Configuration Options
  53  * (easy to change)
  54  */
  55
  56 #define CONFIG_750FX                    /* we have a 750FX (override local.h) */
  57
  58 #define CONFIG_CPCI750          1       /* this is an CPCI750 board     */
  59
  60 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600      */
  61
  62 #undef  CONFIG_ECC                      /* enable ECC support */
  63
  64 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  65
  66 /* which initialization functions to call for this board */
  67 #define CONFIG_MISC_INIT_R
  68 #define CONFIG_BOARD_PRE_INIT
  69 #define CONFIG_BOARD_EARLY_INIT_F 1
  70
  71 #define CONFIG_SYS_BOARD_NAME           "CPCI750"
  72 #define CONFIG_IDENT_STRING     "Marvell 64360 + IBM750FX"
  73
  74 /*#define CONFIG_SYS_HUSH_PARSER*/
  75 #define CONFIG_SYS_HUSH_PARSER
  76
  77 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
  78
  79 #define CONFIG_AUTO_COMPLETE 1
  80
  81 /* Define which ETH port will be used for connecting the network */
  82 #define CONFIG_SYS_ETH_PORT             ETH_0
  83
  84 /*
  85  * The following defines let you select what serial you want to use
  86  * for your console driver.
  87  *
  88  * what to do:
  89  * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
  90  * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
  91  * to 0 below.
  92  *
  93  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  94  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  95  */
  96 #define CONFIG_MPSC
  97 #define CONFIG_MPSC_PORT        0
  98
  99 /* to change the default ethernet port, use this define (options: 0, 1, 2) */
 100 #define CONFIG_NET_MULTI
 101 #define MV_ETH_DEVS             1
 102 #define CONFIG_ETHER_PORT       0
 103
 104 #undef CONFIG_ETHER_PORT_MII    /* use RMII */
 105
 106 #define CONFIG_BOOTDELAY        5       /* autoboot disabled            */
 107
 108 #define CONFIG_RTC_M48T35A      1       /* ST Electronics M48 timekeeper */
 109
 110 #define CONFIG_ZERO_BOOTDELAY_CHECK
 111
 112
 113 #undef  CONFIG_BOOTARGS
 114
 115 /* -----------------------------------------------------------------------------
 116  * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
 117  */
 118
 119 #define CONFIG_IPADDR           "192.168.0.185"
 120
 121 #define CONFIG_SERIAL           "AA000001"
 122 #define CONFIG_SERVERIP         "10.0.0.79"
 123 #define CONFIG_ROOTPATH         "/export/nfs_cpci750/%s"
 124
 125 #define CONFIG_TESTDRAMDATA     y
 126 #define CONFIG_TESTDRAMADDRESS  n
 127 #define CONFIG_TESETDRAMWALK    n
 128
 129 /* ----------------------------------------------------------------------------- */
 130
 131
 132 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 133 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate changes       */
 134
 135 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 136 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
 137
 138 /*
 139  * BOOTP options
 140  */
 141 #define CONFIG_BOOTP_SUBNETMASK
 142 #define CONFIG_BOOTP_GATEWAY
 143 #define CONFIG_BOOTP_HOSTNAME
 144 #define CONFIG_BOOTP_BOOTPATH
 145 #define CONFIG_BOOTP_BOOTFILESIZE
 146
 147
 148 /*
 149  * Command line configuration.
 150  */
 151 #include <config_cmd_default.h>
 152
 153 #define CONFIG_CMD_ASKENV
 154 #define CONFIG_CMD_I2C
 155 #define CONFIG_CMD_CACHE
 156 #define CONFIG_CMD_EEPROM
 157 #define CONFIG_CMD_PCI
 158 #define CONFIG_CMD_ELF
 159 #define CONFIG_CMD_DATE
 160 #define CONFIG_CMD_NET
 161 #define CONFIG_CMD_PING
 162 #define CONFIG_CMD_IDE
 163 #define CONFIG_CMD_FAT
 164 #define CONFIG_CMD_EXT2
 165
 166
 167 #define CONFIG_DOS_PARTITION
 168
 169 #define CONFIG_USE_CPCIDVI
 170
 171 #ifdef  CONFIG_USE_CPCIDVI
 172 #define CONFIG_VIDEO
 173 #define CONFIG_VIDEO_CT69000
 174 #define CONFIG_CFB_CONSOLE
 175 #define CONFIG_VIDEO_SW_CURSOR
 176 #define CONFIG_VIDEO_LOGO
 177 #define CONFIG_I8042_KBD
 178 #define CONFIG_SYS_ISA_IO 0
 179 #endif
 180
 181 /*
 182  * Miscellaneous configurable options
 183  */
 184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 185 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 186 #define CONFIG_SYS_I2C_SPEED    80000           /* I2C speed default */
 187
 188 #define CONFIG_SYS_GT_DUAL_CPU                  /* also for JTAG even with one cpu */
 189 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 190 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 191 #if defined(CONFIG_CMD_KGDB)
 192 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 193 #else
 194 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 195 #endif
 196 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 197 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 198 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 199
 200 /*#define CONFIG_SYS_MEMTEST_START      0x00400000*/    /* memtest works on     */
 201 /*#define CONFIG_SYS_MEMTEST_END                0x00C00000*/    /* 4 ... 12 MB in DRAM  */
 202 /*#define CONFIG_SYS_MEMTEST_END                0x07c00000*/    /* 4 ... 124 MB in DRAM */
 203
 204 /*
 205 #define CONFIG_SYS_DRAM_TEST
 206  * DRAM tests
 207  *   CONFIG_SYS_DRAM_TEST - enables the following tests.
 208  *
 209  *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
 210  *                        Environment variable 'test_dram_data' must be
 211  *                        set to 'y'.
 212  *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
 213  *                        addressable. Environment variable
 214  *                        'test_dram_address' must be set to 'y'.
 215  *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 216  *                        This test takes about 6 minutes to test 64 MB.
 217  *                        Environment variable 'test_dram_walk' must be
 218  *                        set to 'y'.
 219  */
 220 #define CONFIG_SYS_DRAM_TEST
 221 #if defined(CONFIG_SYS_DRAM_TEST)
 222 #define CONFIG_SYS_MEMTEST_START                0x00400000      /* memtest works on     */
 223 /*#define CONFIG_SYS_MEMTEST_END                0x00C00000*/    /* 4 ... 12 MB in DRAM  */
 224 #define CONFIG_SYS_MEMTEST_END          0x07c00000      /* 4 ... 124 MB in DRAM */
 225 #define CONFIG_SYS_DRAM_TEST_DATA
 226 #define CONFIG_SYS_DRAM_TEST_ADDRESS
 227 #define CONFIG_SYS_DRAM_TEST_WALK
 228 #endif /* CONFIG_SYS_DRAM_TEST */
 229
 230 #define CONFIG_DISPLAY_MEMMAP           /* at the end of the bootprocess show the memory map */
 231 #undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT      /* show SPD content during boot */
 232
 233 #define CONFIG_SYS_LOAD_ADDR            0x00300000      /* default load address */
 234
 235 #define CONFIG_SYS_HZ                   1000            /* decr freq: 1ms ticks */
 236 #define CONFIG_SYS_BUS_HZ               133000000       /* 133 MHz (CPU = 5*Bus = 666MHz)               */
 237 #define CONFIG_SYS_BUS_CLK              CONFIG_SYS_BUS_HZ
 238
 239 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 240
 241 #define CONFIG_SYS_TCLK         133000000
 242
 243 /*#define CONFIG_SYS_750FX_HID0         0x8000c084*/
 244 #define CONFIG_SYS_750FX_HID0           0x80008484
 245 #define CONFIG_SYS_750FX_HID1           0x54800000
 246 #define CONFIG_SYS_750FX_HID2           0x00000000
 247
 248 /*
 249  * Low Level Configuration Settings
 250  * (address mappings, register initial values, etc.)
 251  * You should know what you are doing if you make changes here.
 252  */
 253
 254 /*-----------------------------------------------------------------------
 255  * Definitions for initial stack pointer and data area
 256  */
 257
 258  /*
 259  * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
 260  * To an unused memory region. The stack will remain in cache until RAM
 261  * is initialized
 262 */
 263 #undef    CONFIG_SYS_INIT_RAM_LOCK
 264 /* #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000*/ /* unused memory region */
 265 /* #define CONFIG_SYS_INIT_RAM_ADDR     0xfba00000*/ /* unused memory region */
 266 #define CONFIG_SYS_INIT_RAM_ADDR        0xf1080000 /* unused memory region */
 267 #define CONFIG_SYS_INIT_RAM_END 0x1000
 268 #define CONFIG_SYS_GBL_DATA_SIZE        128  /* size in bytes reserved for init data */
 269 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 270
 271 #define RELOCATE_INTERNAL_RAM_ADDR
 272 #ifdef RELOCATE_INTERNAL_RAM_ADDR
 273 /*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
 274 #define CONFIG_SYS_INTERNAL_RAM_ADDR    0xf1080000
 275 #endif
 276
 277 /*-----------------------------------------------------------------------
 278  * Start addresses for the final memory configuration
 279  * (Set up by the startup code)
 280  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 281  */
 282 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 283 /* Dummies for BAT 4-7 */
 284 #define CONFIG_SYS_SDRAM1_BASE          0x10000000      /* each 256 MByte */
 285 #define CONFIG_SYS_SDRAM2_BASE          0x20000000
 286 #define CONFIG_SYS_SDRAM3_BASE          0x30000000
 287 #define CONFIG_SYS_SDRAM4_BASE          0x40000000
 288 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 289 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 290 #define CONFIG_SYS_MONITOR_BASE 0xfff00000
 291 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 256 kB for malloc */
 292
 293 /*-----------------------------------------------------------------------
 294  * FLASH related
 295  *----------------------------------------------------------------------*/
 296
 297 #define CONFIG_FLASH_CFI_DRIVER
 298 #define CONFIG_SYS_FLASH_CFI            1          /* Flash is CFI conformant           */
 299 #define CONFIG_SYS_FLASH_PROTECTION     1          /* use hardware protection           */
 300 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1        /* use buffered writes (20x faster)  */
 301 #define CONFIG_SYS_FLASH_BASE           0xfc000000 /* start of flash banks              */
 302 #define CONFIG_SYS_MAX_FLASH_BANKS      4          /* max number of memory banks        */
 303 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000 /* size of  flash bank               */
 304 #define CONFIG_SYS_MAX_FLASH_SECT       128        /* max number of sectors on one chip */
 305 #define CONFIG_SYS_FLASH_BANKS_LIST  { CONFIG_SYS_FLASH_BASE,                              \
 306                                 CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT,      \
 307                                 CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT,      \
 308                                 CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
 309 #define CONFIG_SYS_FLASH_EMPTY_INFO     1          /* show if bank is empty             */
 310
 311 /* areas to map different things with the GT in physical space */
 312 #define CONFIG_SYS_DRAM_BANKS           4
 313
 314 /* What to put in the bats. */
 315 #define CONFIG_SYS_MISC_REGION_BASE     0xf0000000
 316
 317 /* Peripheral Device section */
 318
 319 /*******************************************************/
 320 /* We have on the cpci750 Board :                      */
 321 /* GT-Chipset Register Area                            */
 322 /* GT-Chipset internal SRAM 256k                       */
 323 /* SRAM on external device module                      */
 324 /* Real time clock on external device module           */
 325 /* dobble UART on external device module               */
 326 /* Data flash on external device module                */
 327 /* Boot flash on external device module                */
 328 /*******************************************************/
 329 #define CONFIG_SYS_DFL_GT_REGS          0x14000000                              /* boot time GT_REGS */
 330 #define  CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000                               /* After power on Reset the CPCI750 is here */
 331
 332 #undef  MARVEL_STANDARD_CFG
 333 #ifndef         MARVEL_STANDARD_CFG
 334 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 335 #define CONFIG_SYS_GT_REGS              0xf1000000                              /* GT Registers will be mapped here */
 336 /*#define CONFIG_SYS_DEV_BASE           0xfc000000*/                            /* GT Devices CS start here */
 337 #define CONFIG_SYS_INT_SRAM_BASE        0xf1080000                              /* GT offers 256k internal fast SRAM */
 338
 339 #define CONFIG_SYS_BOOT_SPACE           0xff000000                              /* BOOT_CS0 flash 0    */
 340 #define CONFIG_SYS_DEV0_SPACE           0xfc000000                              /* DEV_CS0 flash 1     */
 341 #define CONFIG_SYS_DEV1_SPACE           0xfd000000                              /* DEV_CS1 flash 2     */
 342 #define CONFIG_SYS_DEV2_SPACE           0xfe000000                              /* DEV_CS2 flash 3     */
 343 #define CONFIG_SYS_DEV3_SPACE           0xf0000000                              /* DEV_CS3 nvram/can   */
 344
 345 #define CONFIG_SYS_BOOT_SIZE            _16M                                    /* cpci750 flash 0     */
 346 #define CONFIG_SYS_DEV0_SIZE            _16M                                    /* cpci750 flash 1     */
 347 #define CONFIG_SYS_DEV1_SIZE            _16M                                    /* cpci750 flash 2     */
 348 #define CONFIG_SYS_DEV2_SIZE            _16M                                    /* cpci750 flash 3     */
 349 #define CONFIG_SYS_DEV3_SIZE            _16M                                    /* cpci750 nvram/can   */
 350
 351 /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
 352 #endif
 353
 354 /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
 355 #define CONFIG_SYS_DEV0_PAR             0x8FDFFFFF                              /* 16 bit flash */
 356 #define CONFIG_SYS_DEV1_PAR             0x8FDFFFFF                              /* 16 bit flash */
 357 #define CONFIG_SYS_DEV2_PAR             0x8FDFFFFF                              /* 16 bit flash */
 358 #define CONFIG_SYS_DEV3_PAR             0x8FCFFFFF                              /* nvram/can    */
 359 #define CONFIG_SYS_BOOT_PAR             0x8FDFFFFF                              /* 16 bit flash */
 360
 361         /*   c    4    a      8     2     4    1      c         */
 362         /* 33 22|2222|22 22|111 1|11 11|1 1  |    |             */
 363         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210       */
 364         /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100       */
 365         /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4        */
 366
 367
 368 /* MPP Control MV64360 Appendix P P. 632*/
 369 #define CONFIG_SYS_MPP_CONTROL_0        0x00002222      /*                                   */
 370 #define CONFIG_SYS_MPP_CONTROL_1        0x11110000      /*                                   */
 371 #define CONFIG_SYS_MPP_CONTROL_2        0x11111111      /*                                   */
 372 #define CONFIG_SYS_MPP_CONTROL_3        0x00001111      /*                                   */
 373 /* #define CONFIG_SYS_SERIAL_PORT_MUX   0x00000102*/    /*                                   */
 374
 375
 376 #define CONFIG_SYS_GPP_LEVEL_CONTROL    0xffffffff      /* 1111 1111 1111 1111 1111 1111 1111 1111*/
 377
 378 /* setup new config_value for MV64360 DDR-RAM To_do !! */
 379 /*# define CONFIG_SYS_SDRAM_CONFIG      0xd8e18200*/    /* 0x448 */
 380 /*# define CONFIG_SYS_SDRAM_CONFIG      0xd8e14400*/    /* 0x1400 */
 381                                 /* GB has high prio.
 382                                    idma has low prio
 383                                    MPSC has low prio
 384                                    pci has low prio 1 and 2
 385                                    cpu has high prio
 386                                    Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
 387                                    ECC disable
 388                                    non registered DRAM */
 389                                 /* 31:26   25:22  21:20 19 18 17 16 */
 390                                 /* 100001 0000   010   0   0   0  0 */
 391                                 /* refresh_count=0x400
 392                                    phisical interleaving disable
 393                                    virtual interleaving enable */
 394                                 /* 15 14 13:0 */
 395                                 /* 0  1  0x400 */
 396 # define CONFIG_SYS_SDRAM_CONFIG        0x58200400      /* 0x1400  copied from Dink32 bzw. VxWorks*/
 397
 398
 399 /*-----------------------------------------------------------------------
 400  * PCI stuff
 401  *-----------------------------------------------------------------------
 402  */
 403
 404 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 405 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 406 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 407
 408 #define CONFIG_PCI                      /* include pci support          */
 409 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 410 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 411 #define CONFIG_PCI_SCAN_SHOW            /* show devices on bus          */
 412
 413 /* PCI MEMORY MAP section */
 414 #define CONFIG_SYS_PCI0_MEM_BASE        0x80000000
 415 #define CONFIG_SYS_PCI0_MEM_SIZE        _128M
 416 #define CONFIG_SYS_PCI1_MEM_BASE        0x88000000
 417 #define CONFIG_SYS_PCI1_MEM_SIZE        _128M
 418
 419 #define CONFIG_SYS_PCI0_0_MEM_SPACE     (CONFIG_SYS_PCI0_MEM_BASE)
 420 #define CONFIG_SYS_PCI1_0_MEM_SPACE     (CONFIG_SYS_PCI1_MEM_BASE)
 421
 422 /* PCI I/O MAP section */
 423 #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
 424 #define CONFIG_SYS_PCI0_IO_SIZE _16M
 425 #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
 426 #define CONFIG_SYS_PCI1_IO_SIZE _16M
 427
 428 #define CONFIG_SYS_PCI0_IO_SPACE        (CONFIG_SYS_PCI0_IO_BASE)
 429 #define CONFIG_SYS_PCI0_IO_SPACE_PCI    0x00000000
 430 #define CONFIG_SYS_PCI1_IO_SPACE        (CONFIG_SYS_PCI1_IO_BASE)
 431 #define CONFIG_SYS_PCI1_IO_SPACE_PCI    0x00000000
 432
 433 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
 434
 435 #if defined (CONFIG_750CX)
 436 #define CONFIG_SYS_PCI_IDSEL 0x0
 437 #else
 438 #define CONFIG_SYS_PCI_IDSEL 0x30
 439 #endif
 440
 441 /*-----------------------------------------------------------------------
 442  * IDE/ATA stuff
 443  *-----------------------------------------------------------------------
 444  */
 445 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 446 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 447 #define CONFIG_IDE_RESET                /* no reset for ide supported   */
 448 #define CONFIG_IDE_PREINIT              /* check for units              */
 449
 450 #define CONFIG_SYS_IDE_MAXBUS           2               /* max. 1 IDE busses    */
 451 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
 452
 453 #define CONFIG_SYS_ATA_BASE_ADDR        0
 454 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 455 #define CONFIG_SYS_ATA_IDE1_OFFSET      0
 456
 457 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 458 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 459 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 460
 461
 462 /*----------------------------------------------------------------------
 463  * Initial BAT mappings
 464  */
 465
 466 /* NOTES:
 467  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 468  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 469  */
 470
 471 /* SDRAM */
 472 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 473 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 474 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 475 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 476
 477 /* init ram */
 478 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 479 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
 480 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 481 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 482
 483 /* PCI0, PCI1 in one BAT */
 484 #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
 485 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
 486 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 487 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 488
 489 /* GT regs, bootrom, all the devices, PCI I/O */
 490 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 491 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 492 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 493 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 494
 495 /*
 496  * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
 497  * IBAT4 and DBAT4
 498  * FIXME: ingo disable BATs for Linux Kernel
 499  */
 500 #undef SETUP_HIGH_BATS_FX750            /* don't initialize BATS 4-7 */
 501 /*#define SETUP_HIGH_BATS_FX750*/               /* initialize BATS 4-7 */
 502
 503 #ifdef SETUP_HIGH_BATS_FX750
 504 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 505 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 506 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 507 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
 508
 509 /* IBAT5 and DBAT5 */
 510 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 511 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 512 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 513 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
 514
 515 /* IBAT6 and DBAT6 */
 516 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 517 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 518 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 519 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
 520
 521 /* IBAT7 and DBAT7 */
 522 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 523 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 524 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 525 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
 526
 527 #else           /* set em out of range for Linux !!!!!!!!!!! */
 528 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 529 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 530 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 531 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
 532
 533 /* IBAT5 and DBAT5 */
 534 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 535 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 536 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 537 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
 538
 539 /* IBAT6 and DBAT6 */
 540 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 541 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 542 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 543 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
 544
 545 /* IBAT7 and DBAT7 */
 546 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 547 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 548 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 549 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
 550
 551 #endif
 552 /* FIXME: ingo end: disable BATs for Linux Kernel */
 553
 554 /* I2C addresses for the two DIMM SPD chips */
 555 #define DIMM0_I2C_ADDR  0x51
 556 #define DIMM1_I2C_ADDR  0x52
 557
 558 /*
 559  * For booting Linux, the board info and command line data
 560  * have to be in the first 8 MB of memory, since this is
 561  * the maximum mapped by the Linux kernel during initialization.
 562  */
 563 #define CONFIG_SYS_BOOTMAPSZ            (8<<20) /* Initial Memory map for Linux */
 564
 565 /*-----------------------------------------------------------------------
 566  * FLASH organization
 567  */
 568 #define CONFIG_SYS_BOOT_FLASH_WIDTH     2       /* 16 bit */
 569
 570 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 571 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 572 #define CONFIG_SYS_FLASH_LOCK_TOUT      500     /* Timeout for Flash Lock (in ms) */
 573
 574 #if 0
 575 #define CONFIG_ENV_IS_IN_FLASH
 576 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector */
 577 #define CONFIG_ENV_SECT_SIZE    0x10000
 578 #define CONFIG_ENV_ADDR         0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
 579 /* #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
 580 #endif
 581
 582 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 583 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
 584 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
 585 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x050
 586 #define CONFIG_ENV_OFFSET               0x200   /* environment starts at the beginning of the EEPROM */
 587 #define CONFIG_ENV_SIZE         0x600   /* 2048 bytes may be used for env vars*/
 588
 589 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0000000              /* NVRAM base address   */
 590 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)               /* NVRAM size           */
 591 #define CONFIG_SYS_VXWORKS_MAC_PTR      (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
 592
 593 /*-----------------------------------------------------------------------
 594  * Cache Configuration
 595  */
 596 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For all MPC74xx CPUs          */
 597 #if defined(CONFIG_CMD_KGDB)
 598 #define CONFIG_SYS_CACHELINE_SHIFT      5       /* log base 2 of the above value */
 599 #endif
 600
 601 /*-----------------------------------------------------------------------
 602  * L2CR setup -- make sure this is right for your board!
 603  * look in include/mpc74xx.h for the defines used here
 604  */
 605
 606 /*#define CONFIG_SYS_L2*/
 607 #undef CONFIG_SYS_L2
 608
 609 /*    #ifdef CONFIG_750CX*/
 610 #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
 611 #define L2_INIT 0
 612 #else
 613 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 614                         L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 615 #endif
 616
 617 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 618
 619 /*
 620  * Internal Definitions
 621  *
 622  * Boot Flags
 623  */
 624 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 625 #define BOOTFLAG_WARM   0x02            /* Software reboot                  */
 626
 627 #define CONFIG_SYS_BOARD_ASM_INIT       1
 628
 629 #endif  /* __CONFIG_H */