include/configs/CPCIISER4.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_CPCIISER4        1       /* ...on a CPCIISER4 board      */
  39
  40 #define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
  41
  42 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  43
  44 #define CONFIG_BAUDRATE         9600
  45 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  46
  47 #undef  CONFIG_BOOTARGS
  48 #define CONFIG_BOOTCOMMAND      "bootm fff00000"
  49
  50 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  51 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  52
  53 #define CONFIG_MII              1       /* MII PHY management           */
  54 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  55
  56 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  57                                 CFG_CMD_PCI     | \
  58                                 CFG_CMD_IRQ     | \
  59                                 CFG_CMD_MII     | \
  60                                 CFG_CMD_ELF     | \
  61                                 CFG_CMD_EEPROM  )
  62
  63 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  64 #include <cmd_confdefs.h>
  65
  66 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  67
  68 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  69
  70 /*
  71  * Miscellaneous configurable options
  72  */
  73 #define CFG_LONGHELP                    /* undef to save memory         */
  74 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  75 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  76 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
  77 #else
  78 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  79 #endif
  80 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  81 #define CFG_MAXARGS     16              /* max number of command args   */
  82 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
  83
  84 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
  85
  86 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
  87 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
  88
  89 #define CFG_EXT_SERIAL_CLOCK    1843200  /* use external serial clock   */
  90
  91 /* The following table includes the supported baudrates */
  92 #define CFG_BAUDRATE_TABLE      \
  93         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
  94          57600, 115200, 230400, 460800, 921600 }
  95
  96 #define CFG_LOAD_ADDR   0x100000        /* default load address */
  97 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
  98
  99 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 100
 101 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 102
 103 /*-----------------------------------------------------------------------
 104  * PCI stuff
 105  *-----------------------------------------------------------------------
 106  */
 107 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 108 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 109 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 110
 111 #define CONFIG_PCI                      /* include pci support          */
 112 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 113 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 114                                         /* resource configuration       */
 115
 116 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 117 #define CFG_PCI_SUBSYS_DEVICEID 0x0404  /* PCI Device ID: CPCI-ISER4    */
 118 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 119 #define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
 120 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 121 #define CFG_PCI_PTM2LA  0xffe00000      /* point to flash               */
 122 #define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
 123 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 124
 125 /*-----------------------------------------------------------------------
 126  * Start addresses for the final memory configuration
 127  * (Set up by the startup code)
 128  * Please note that CFG_SDRAM_BASE _must_ start at 0
 129  */
 130 #define CFG_SDRAM_BASE          0x00000000
 131 #define CFG_FLASH_BASE          0xFFFC0000
 132 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 133 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 134 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 135
 136 /*
 137  * For booting Linux, the board info and command line data
 138  * have to be in the first 8 MB of memory, since this is
 139  * the maximum mapped by the Linux kernel during initialization.
 140  */
 141 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 142 /*-----------------------------------------------------------------------
 143  * FLASH organization
 144  */
 145 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 146 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 147
 148 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 149 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 150
 151 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 152 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 153 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 154 /*
 155  * The following defines are added for buggy IOP480 byte interface.
 156  * All other boards should use the standard values (CPCI405 etc.)
 157  */
 158 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 159 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 160 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 161
 162 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 163
 164 /*-----------------------------------------------------------------------
 165  * I2C EEPROM (CAT24WC08) for environment
 166  */
 167 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 168 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 169 #define CFG_I2C_SLAVE           0x7F
 170
 171 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 172 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 173 /* mask of address bits that overflow into the "EEPROM chip address"    */
 174 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 175 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 176                                         /* 16 byte page write mode using*/
 177                                         /* last 4 bits of the address   */
 178 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 179 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 180
 181 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 182 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 183 #define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
 184                                    /* total size of a CAT24WC08 is 1024 bytes */
 185
 186 /*-----------------------------------------------------------------------
 187  * Cache Configuration
 188  */
 189 #define CFG_DCACHE_SIZE         8192    /* For IBM 405 CPUs                     */
 190 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 191 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 192 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 193 #endif
 194
 195 /*
 196  * Init Memory Controller:
 197  *
 198  * BR0/1 and OR0/1 (FLASH)
 199  */
 200
 201 #define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 202 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 203
 204 /*-----------------------------------------------------------------------
 205  * External Bus Controller (EBC) Setup
 206  */
 207
 208 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 209 #define CFG_EBC_PB0AP           0x92015480
 210 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 211
 212 /* Memory Bank 1 (Uart 8bit) initialization                                     */
 213 #define CFG_EBC_PB1AP           0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1  */
 214 #define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 215
 216 /* Memory Bank 2 (Uart 32bit) initialization                                    */
 217 #define CFG_EBC_PB2AP           0x000004c0  /* no Ready, BEM=1                  */
 218 #define CFG_EBC_PB2CR           0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 219
 220 /* Memory Bank 3 (FPGA Reset) initialization                                    */
 221 #define CFG_EBC_PB3AP           0x010004C0  /* no Ready, BEM=1                  */
 222 #define CFG_EBC_PB3CR           0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 223
 224 /*-----------------------------------------------------------------------
 225  * Definitions for initial stack pointer and data area (in DPRAM)
 226  */
 227 #define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
 228 #define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
 229 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 230 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 231 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 232 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 233
 234 /*
 235  * Internal Definitions
 236  *
 237  * Boot Flags
 238  */
 239 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 240 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 241
 242 #endif  /* __CONFIG_H */