include/configs/CPU86.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  37 #define CONFIG_CPU86            1       /* ...on a CPU86 board  */
  38 #define CONFIG_CPM2             1       /* Has a CPM2 */
  39
  40 /*
  41  * select serial console configuration
  42  *
  43  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  44  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  45  * for SCC).
  46  *
  47  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  48  * defined elsewhere (for example, on the cogent platform, there are serial
  49  * ports on the motherboard which are used for the serial console - see
  50  * cogent/cma101/serial.[ch]).
  51  */
  52 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  53 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  54 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  55 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  56
  57 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  58 #define CONFIG_BAUDRATE         230400
  59 #else
  60 #define CONFIG_BAUDRATE         9600
  61 #endif
  62
  63 /*
  64  * select ethernet configuration
  65  *
  66  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  67  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  68  * for FCC)
  69  *
  70  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  71  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  72  */
  73 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  74 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  75 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  76 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  77
  78 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  79
  80 /*
  81  * - Rx-CLK is CLK11
  82  * - Tx-CLK is CLK12
  83  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  84  * - Enable Full Duplex in FSMR
  85  */
  86 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  87 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  88 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  89 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  90
  91 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  92
  93 /*
  94  * - Rx-CLK is CLK13
  95  * - Tx-CLK is CLK14
  96  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  97  * - Enable Full Duplex in FSMR
  98  */
  99 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 100 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 101 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 102 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 103
 104 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 105
 106 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 107 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
 108
 109 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 110
 111 #define CONFIG_PREBOOT                                                          \
 112         "echo; "                                                                \
 113         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 114         "echo"
 115
 116 #undef  CONFIG_BOOTARGS
 117 #define CONFIG_BOOTCOMMAND                                                      \
 118         "bootp; "                                                               \
 119         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 120         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 121         "bootm"
 122
 123 /*-----------------------------------------------------------------------
 124  * I2C/EEPROM/RTC configuration
 125  */
 126 #define CONFIG_SOFT_I2C                 /* Software I2C support enabled */
 127
 128 # define CONFIG_SYS_I2C_SPEED           50000
 129 # define CONFIG_SYS_I2C_SLAVE           0xFE
 130 /*
 131  * Software (bit-bang) I2C driver configuration
 132  */
 133 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 134 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 135 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 136 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 137 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 138                         else    iop->pdat &= ~0x00010000
 139 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 140                         else    iop->pdat &= ~0x00020000
 141 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 142
 143 #define CONFIG_RTC_PCF8563
 144 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 145
 146 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 147
 148 /*-----------------------------------------------------------------------
 149  * Miscellaneous configuration options
 150  */
 151
 152 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 153 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 154
 155 /*
 156  * BOOTP options
 157  */
 158 #define CONFIG_BOOTP_SUBNETMASK
 159 #define CONFIG_BOOTP_GATEWAY
 160 #define CONFIG_BOOTP_HOSTNAME
 161 #define CONFIG_BOOTP_BOOTPATH
 162 #define CONFIG_BOOTP_BOOTFILESIZE
 163
 164
 165 /*
 166  * Command line configuration.
 167  */
 168 #include <config_cmd_default.h>
 169
 170 #define CONFIG_CMD_BEDBUG
 171 #define CONFIG_CMD_DATE
 172 #define CONFIG_CMD_DHCP
 173 #define CONFIG_CMD_EEPROM
 174 #define CONFIG_CMD_I2C
 175 #define CONFIG_CMD_NFS
 176 #define CONFIG_CMD_SNTP
 177
 178
 179 /*
 180  * Miscellaneous configurable options
 181  */
 182 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 183 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 184 #if defined(CONFIG_CMD_KGDB)
 185 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 186 #else
 187 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 188 #endif
 189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 190 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 191 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 192
 193 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 194 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 195
 196 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 197
 198 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 199
 200 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 201
 202 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 203
 204 /*
 205  * For booting Linux, the board info and command line data
 206  * have to be in the first 8 MB of memory, since this is
 207  * the maximum mapped by the Linux kernel during initialization.
 208  */
 209 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 210
 211 /*-----------------------------------------------------------------------
 212  * Flash configuration
 213  */
 214
 215 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 216 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 217 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 218 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 219
 220 /*-----------------------------------------------------------------------
 221  * FLASH organization
 222  */
 223 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 224 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 225
 226 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 227 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 228
 229 /*-----------------------------------------------------------------------
 230  * Other areas to be mapped
 231  */
 232
 233 /* CS3: Dual ported SRAM */
 234 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 235 #define CONFIG_SYS_DPSRAM_SIZE          0x00020000
 236
 237 /* CS4: DiskOnChip */
 238 #define CONFIG_SYS_DOC_BASE             0xF4000000
 239 #define CONFIG_SYS_DOC_SIZE             0x00100000
 240
 241 /* CS5: FDC37C78 controller */
 242 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 243 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 244
 245 /* CS6: Board configuration registers */
 246 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 247 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 248
 249 /* CS7: VME Extended Access Range */
 250 #define CONFIG_SYS_VMEEAR_BASE          0x80000000
 251 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 252
 253 /* CS8: VME Standard Access Range */
 254 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 255 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 256
 257 /* CS9: VME Short I/O Access Range */
 258 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 259 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 260
 261 /*-----------------------------------------------------------------------
 262  * Hard Reset Configuration Words
 263  *
 264  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 265  * defines for the various registers affected by the HRCW e.g. changing
 266  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 267  */
 268 #if defined(CONFIG_BOOT_ROM)
 269 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 270                                  HRCW_BPS01 | HRCW_CS10PC01)
 271 #else
 272 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 273 #endif
 274
 275 /* no slaves so just fill with zeros */
 276 #define CONFIG_SYS_HRCW_SLAVE1          0
 277 #define CONFIG_SYS_HRCW_SLAVE2          0
 278 #define CONFIG_SYS_HRCW_SLAVE3          0
 279 #define CONFIG_SYS_HRCW_SLAVE4          0
 280 #define CONFIG_SYS_HRCW_SLAVE5          0
 281 #define CONFIG_SYS_HRCW_SLAVE6          0
 282 #define CONFIG_SYS_HRCW_SLAVE7          0
 283
 284 /*-----------------------------------------------------------------------
 285  * Internal Memory Mapped Register
 286  */
 287 #define CONFIG_SYS_IMMR         0xF0000000
 288
 289 /*-----------------------------------------------------------------------
 290  * Definitions for initial stack pointer and data area (in DPRAM)
 291  */
 292 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 293 #define CONFIG_SYS_INIT_RAM_END 0x4000  /* End of used area in DPRAM    */
 294 #define CONFIG_SYS_GBL_DATA_SIZE        128 /* size in bytes reserved for initial data*/
 295 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 296 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 297
 298 /*-----------------------------------------------------------------------
 299  * Start addresses for the final memory configuration
 300  * (Set up by the startup code)
 301  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 302  *
 303  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 304  */
 305 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 306 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 307 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 308 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 309 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 310
 311 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 312 # define CONFIG_SYS_RAMBOOT
 313 #endif
 314
 315 #if 0
 316 /* environment is in Flash */
 317 #define CONFIG_ENV_IS_IN_FLASH  1
 318 #ifdef CONFIG_BOOT_ROM
 319 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 320 # define CONFIG_ENV_SIZE                0x10000
 321 # define CONFIG_ENV_SECT_SIZE   0x10000
 322 #endif
 323 #else
 324 /* environment is in EEPROM */
 325 #define CONFIG_ENV_IS_IN_EEPROM 1
 326 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 328 /* mask of address bits that overflow into the "EEPROM chip address"    */
 329 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 330 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 331 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 332 #define CONFIG_ENV_OFFSET               512
 333 #define CONFIG_ENV_SIZE         (2048 - 512)
 334 #endif
 335
 336 /*
 337  * Internal Definitions
 338  *
 339  * Boot Flags
 340  */
 341 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 342 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 343
 344
 345 /*-----------------------------------------------------------------------
 346  * Cache Configuration
 347  */
 348 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 349 #if defined(CONFIG_CMD_KGDB)
 350 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 351 #endif
 352
 353 /*-----------------------------------------------------------------------
 354  * HIDx - Hardware Implementation-dependent Registers                    2-11
 355  *-----------------------------------------------------------------------
 356  * HID0 also contains cache control - initially enable both caches and
 357  * invalidate contents, then the final state leaves only the instruction
 358  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 359  * but Soft reset does not.
 360  *
 361  * HID1 has only read-only information - nothing to set.
 362  */
 363 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 364                          HID0_DCI|HID0_IFEM|HID0_ABE)
 365 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 366 #define CONFIG_SYS_HID2        0
 367
 368 /*-----------------------------------------------------------------------
 369  * RMR - Reset Mode Register                                     5-5
 370  *-----------------------------------------------------------------------
 371  * turn on Checkstop Reset Enable
 372  */
 373 #define CONFIG_SYS_RMR         RMR_CSRE
 374
 375 /*-----------------------------------------------------------------------
 376  * BCR - Bus Configuration                                       4-25
 377  *-----------------------------------------------------------------------
 378  */
 379 #define BCR_APD01       0x10000000
 380 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 381
 382 /*-----------------------------------------------------------------------
 383  * SIUMCR - SIU Module Configuration                             4-31
 384  *-----------------------------------------------------------------------
 385  */
 386 #define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 387                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 388
 389 /*-----------------------------------------------------------------------
 390  * SYPCR - System Protection Control                             4-35
 391  * SYPCR can only be written once after reset!
 392  *-----------------------------------------------------------------------
 393  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 394  */
 395 #if defined(CONFIG_WATCHDOG)
 396 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 397                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 398 #else
 399 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 400                          SYPCR_SWRI|SYPCR_SWP)
 401 #endif /* CONFIG_WATCHDOG */
 402
 403 /*-----------------------------------------------------------------------
 404  * TMCNTSC - Time Counter Status and Control                     4-40
 405  *-----------------------------------------------------------------------
 406  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 407  * and enable Time Counter
 408  */
 409 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 410
 411 /*-----------------------------------------------------------------------
 412  * PISCR - Periodic Interrupt Status and Control                 4-42
 413  *-----------------------------------------------------------------------
 414  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 415  * Periodic timer
 416  */
 417 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 418
 419 /*-----------------------------------------------------------------------
 420  * SCCR - System Clock Control                                   9-8
 421  *-----------------------------------------------------------------------
 422  * Ensure DFBRG is Divide by 16
 423  */
 424 #define CONFIG_SYS_SCCR        SCCR_DFBRG01
 425
 426 /*-----------------------------------------------------------------------
 427  * RCCR - RISC Controller Configuration                         13-7
 428  *-----------------------------------------------------------------------
 429  */
 430 #define CONFIG_SYS_RCCR        0
 431
 432 #define CONFIG_SYS_MIN_AM_MASK  0xC0000000
 433 /*-----------------------------------------------------------------------
 434  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 435  *-----------------------------------------------------------------------
 436  */
 437 #define CONFIG_SYS_MPTPR       0x1F00
 438
 439 /*-----------------------------------------------------------------------
 440  * PSRT - Refresh Timer Register                                10-16
 441  *-----------------------------------------------------------------------
 442  */
 443 #define CONFIG_SYS_PSRT        0x0f
 444
 445 /*-----------------------------------------------------------------------
 446  * PSRT - SDRAM Mode Register                                   10-10
 447  *-----------------------------------------------------------------------
 448  */
 449
 450         /* SDRAM initialization values for 8-column chips
 451          */
 452 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 453                          ORxS_BPD_4                     |\
 454                          ORxS_ROWST_PBI0_A9             |\
 455                          ORxS_NUMR_12)
 456
 457 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 458                          PSDMR_BSMA_A14_A16             |\
 459                          PSDMR_SDA10_PBI0_A10           |\
 460                          PSDMR_RFRC_7_CLK               |\
 461                          PSDMR_PRETOACT_2W              |\
 462                          PSDMR_ACTTORW_1W               |\
 463                          PSDMR_LDOTOPRE_1C              |\
 464                          PSDMR_WRC_1C                   |\
 465                          PSDMR_CL_2)
 466
 467         /* SDRAM initialization values for 9-column chips
 468          */
 469 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 470                          ORxS_BPD_4                     |\
 471                          ORxS_ROWST_PBI0_A7             |\
 472                          ORxS_NUMR_13)
 473
 474 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 475                          PSDMR_BSMA_A13_A15             |\
 476                          PSDMR_SDA10_PBI0_A9            |\
 477                          PSDMR_RFRC_7_CLK               |\
 478                          PSDMR_PRETOACT_2W              |\
 479                          PSDMR_ACTTORW_1W               |\
 480                          PSDMR_LDOTOPRE_1C              |\
 481                          PSDMR_WRC_1C                   |\
 482                          PSDMR_CL_2)
 483
 484 /*
 485  * Init Memory Controller:
 486  *
 487  * Bank Bus     Machine PortSz  Device
 488  * ---- ---     ------- ------  ------
 489  *  0   60x     GPCM    8  bit  Boot ROM
 490  *  1   60x     GPCM    64 bit  FLASH
 491  *  2   60x     SDRAM   64 bit  SDRAM
 492  *
 493  */
 494
 495 #define CONFIG_SYS_MRS_OFFS     0x00000000
 496
 497 #ifdef CONFIG_BOOT_ROM
 498 /* Bank 0 - Boot ROM
 499  */
 500 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 501                          BRx_PS_8                       |\
 502                          BRx_MS_GPCM_P                  |\
 503                          BRx_V)
 504
 505 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 506                          ORxG_CSNT                      |\
 507                          ORxG_ACS_DIV1                  |\
 508                          ORxG_SCY_3_CLK                 |\
 509                          ORxU_EHTR_8IDLE)
 510
 511 /* Bank 1 - FLASH
 512  */
 513 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 514                          BRx_PS_64                      |\
 515                          BRx_MS_GPCM_P                  |\
 516                          BRx_V)
 517
 518 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 519                          ORxG_CSNT                      |\
 520                          ORxG_ACS_DIV1                  |\
 521                          ORxG_SCY_3_CLK                 |\
 522                          ORxU_EHTR_8IDLE)
 523
 524 #else /* CONFIG_BOOT_ROM */
 525 /* Bank 0 - FLASH
 526  */
 527 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 528                          BRx_PS_64                      |\
 529                          BRx_MS_GPCM_P                  |\
 530                          BRx_V)
 531
 532 #define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
 533                          ORxG_CSNT                      |\
 534                          ORxG_ACS_DIV1                  |\
 535                          ORxG_SCY_3_CLK                 |\
 536                          ORxU_EHTR_8IDLE)
 537
 538 /* Bank 1 - Boot ROM
 539  */
 540 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 541                          BRx_PS_8                       |\
 542                          BRx_MS_GPCM_P                  |\
 543                          BRx_V)
 544
 545 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
 546                          ORxG_CSNT                      |\
 547                          ORxG_ACS_DIV1                  |\
 548                          ORxG_SCY_3_CLK                 |\
 549                          ORxU_EHTR_8IDLE)
 550
 551 #endif /* CONFIG_BOOT_ROM */
 552
 553
 554 /* Bank 2 - 60x bus SDRAM
 555  */
 556 #ifndef CONFIG_SYS_RAMBOOT
 557 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 558                          BRx_PS_64                      |\
 559                          BRx_MS_SDRAM_P                 |\
 560                          BRx_V)
 561
 562 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
 563
 564 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
 565 #endif /* CONFIG_SYS_RAMBOOT */
 566
 567 /* Bank 3 - Dual Ported SRAM
 568  */
 569 #define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 570                          BRx_PS_16                      |\
 571                          BRx_MS_GPCM_P                  |\
 572                          BRx_V)
 573
 574 #define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
 575                          ORxG_CSNT                      |\
 576                          ORxG_ACS_DIV1                  |\
 577                          ORxG_SCY_5_CLK                 |\
 578                          ORxG_SETA)
 579
 580 /* Bank 4 - DiskOnChip
 581  */
 582 #define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
 583                          BRx_PS_8                       |\
 584                          BRx_MS_GPCM_P                  |\
 585                          BRx_V)
 586
 587 #define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
 588                          ORxG_ACS_DIV2                  |\
 589                          ORxG_SCY_5_CLK                 |\
 590                          ORxU_EHTR_8IDLE)
 591
 592 /* Bank 5 - FDC37C78 controller
 593  */
 594 #define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 595                          BRx_PS_8                         |\
 596                          BRx_MS_GPCM_P                    |\
 597                          BRx_V)
 598
 599 #define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
 600                          ORxG_ACS_DIV2                    |\
 601                          ORxG_SCY_8_CLK                   |\
 602                          ORxU_EHTR_8IDLE)
 603
 604 /* Bank 6 - Board control registers
 605  */
 606 #define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
 607                          BRx_PS_8                       |\
 608                          BRx_MS_GPCM_P                  |\
 609                          BRx_V)
 610
 611 #define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
 612                          ORxG_CSNT                      |\
 613                          ORxG_SCY_5_CLK)
 614
 615 /* Bank 7 - VME Extended Access Range
 616  */
 617 #define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 618                          BRx_PS_32                      |\
 619                          BRx_MS_GPCM_P                  |\
 620                          BRx_V)
 621
 622 #define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
 623                          ORxG_CSNT                      |\
 624                          ORxG_ACS_DIV1                  |\
 625                          ORxG_SCY_5_CLK                 |\
 626                          ORxG_SETA)
 627
 628 /* Bank 8 - VME Standard Access Range
 629  */
 630 #define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 631                          BRx_PS_16                      |\
 632                          BRx_MS_GPCM_P                  |\
 633                          BRx_V)
 634
 635 #define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
 636                          ORxG_CSNT                      |\
 637                          ORxG_ACS_DIV1                  |\
 638                          ORxG_SCY_5_CLK                 |\
 639                          ORxG_SETA)
 640
 641 /* Bank 9 - VME Short I/O Access Range
 642  */
 643 #define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 644                          BRx_PS_16                        |\
 645                          BRx_MS_GPCM_P                    |\
 646                          BRx_V)
 647
 648 #define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
 649                          ORxG_CSNT                        |\
 650                          ORxG_ACS_DIV1                    |\
 651                          ORxG_SCY_5_CLK                   |\
 652                          ORxG_SETA)
 653
 654 #endif  /* __CONFIG_H */