include/configs/CPU86.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  37 #define CONFIG_CPU86            1       /* ...on a CPU86 board  */
  38 #define CONFIG_CPM2             1       /* Has a CPM2 */
  39
  40 /*
  41  * select serial console configuration
  42  *
  43  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  44  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  45  * for SCC).
  46  *
  47  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  48  * defined elsewhere (for example, on the cogent platform, there are serial
  49  * ports on the motherboard which are used for the serial console - see
  50  * cogent/cma101/serial.[ch]).
  51  */
  52 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  53 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  54 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  55 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  56
  57 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  58 #define CONFIG_BAUDRATE         230400
  59 #else
  60 #define CONFIG_BAUDRATE         9600
  61 #endif
  62
  63 /*
  64  * select ethernet configuration
  65  *
  66  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  67  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  68  * for FCC)
  69  *
  70  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  71  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  72  * from CONFIG_COMMANDS to remove support for networking.
  73  *
  74  */
  75 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  76 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  77 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  78 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  79
  80 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  81
  82 /*
  83  * - Rx-CLK is CLK11
  84  * - Tx-CLK is CLK12
  85  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  86  * - Enable Full Duplex in FSMR
  87  */
  88 # define CFG_CMXFCR_MASK        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  89 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  90 # define CFG_CPMFCR_RAMTYPE     0
  91 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
  92
  93 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  94
  95 /*
  96  * - Rx-CLK is CLK13
  97  * - Tx-CLK is CLK14
  98  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  99  * - Enable Full Duplex in FSMR
 100  */
 101 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 102 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 103 # define CFG_CPMFCR_RAMTYPE     0
 104 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 105
 106 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 107
 108 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 109 #define CONFIG_8260_CLKIN       64000000        /* in Hz */
 110
 111 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 112
 113 #define CONFIG_PREBOOT                                                          \
 114         "echo; "                                                                \
 115         "echo Type \"run flash_nfs\" to mount root filesystem over NFS; "       \
 116         "echo"
 117
 118 #undef  CONFIG_BOOTARGS
 119 #define CONFIG_BOOTCOMMAND                                                      \
 120         "bootp; "                                                               \
 121         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 122         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 123         "bootm"
 124
 125 /*-----------------------------------------------------------------------
 126  * I2C/EEPROM/RTC configuration
 127  */
 128 #define CONFIG_SOFT_I2C                 /* Software I2C support enabled */
 129
 130 # define CFG_I2C_SPEED          50000
 131 # define CFG_I2C_SLAVE          0xFE
 132 /*
 133  * Software (bit-bang) I2C driver configuration
 134  */
 135 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 136 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 137 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 138 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 139 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 140                         else    iop->pdat &= ~0x00010000
 141 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 142                         else    iop->pdat &= ~0x00020000
 143 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 144
 145 #define CONFIG_RTC_PCF8563
 146 #define CFG_I2C_RTC_ADDR        0x51
 147
 148 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 149
 150 /*-----------------------------------------------------------------------
 151  * Disk-On-Chip configuration
 152  */
 153
 154 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
 155
 156 #define CFG_DOC_SUPPORT_2000
 157 #define CFG_DOC_SUPPORT_MILLENNIUM
 158
 159 /*-----------------------------------------------------------------------
 160  * Miscellaneous configuration options
 161  */
 162
 163 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 164 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 165
 166 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 167
 168 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 169                                 CFG_CMD_BEDBUG  | \
 170                                 CFG_CMD_DATE    | \
 171                                 CFG_CMD_DHCP    | \
 172                                 CFG_CMD_DOC     | \
 173                                 CFG_CMD_EEPROM  | \
 174                                 CFG_CMD_I2C     | \
 175                                 CFG_CMD_NFS     | \
 176                                 CFG_CMD_SNTP    )
 177
 178 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 179 #include <cmd_confdefs.h>
 180
 181 #define CFG_NAND_LEGACY
 182
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186 #define CFG_LONGHELP                    /* undef to save memory         */
 187 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 188 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 189 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 190 #else
 191 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 192 #endif
 193 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 194 #define CFG_MAXARGS     16              /* max number of command args   */
 195 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 196
 197 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 198 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM  */
 199
 200 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 201
 202 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 203
 204 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 205
 206 #define CFG_RESET_ADDRESS 0xFFF00100    /* "bad" address                */
 207
 208 /*
 209  * For booting Linux, the board info and command line data
 210  * have to be in the first 8 MB of memory, since this is
 211  * the maximum mapped by the Linux kernel during initialization.
 212  */
 213 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 214
 215 /*-----------------------------------------------------------------------
 216  * Flash configuration
 217  */
 218
 219 #define CFG_BOOTROM_BASE        0xFF800000
 220 #define CFG_BOOTROM_SIZE        0x00080000
 221 #define CFG_FLASH_BASE          0xFF000000
 222 #define CFG_FLASH_SIZE          0x00800000
 223
 224 /*-----------------------------------------------------------------------
 225  * FLASH organization
 226  */
 227 #define CFG_MAX_FLASH_BANKS     2       /* max num of memory banks      */
 228 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 229
 230 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 231 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 232
 233 /*-----------------------------------------------------------------------
 234  * Other areas to be mapped
 235  */
 236
 237 /* CS3: Dual ported SRAM */
 238 #define CFG_DPSRAM_BASE         0x40000000
 239 #define CFG_DPSRAM_SIZE         0x00020000
 240
 241 /* CS4: DiskOnChip */
 242 #define CFG_DOC_BASE            0xF4000000
 243 #define CFG_DOC_SIZE            0x00100000
 244
 245 /* CS5: FDC37C78 controller */
 246 #define CFG_FDC37C78_BASE       0xF1000000
 247 #define CFG_FDC37C78_SIZE       0x00100000
 248
 249 /* CS6: Board configuration registers */
 250 #define CFG_BCRS_BASE           0xF2000000
 251 #define CFG_BCRS_SIZE           0x00010000
 252
 253 /* CS7: VME Extended Access Range */
 254 #define CFG_VMEEAR_BASE         0x80000000
 255 #define CFG_VMEEAR_SIZE         0x01000000
 256
 257 /* CS8: VME Standard Access Range */
 258 #define CFG_VMESAR_BASE         0xFE000000
 259 #define CFG_VMESAR_SIZE         0x01000000
 260
 261 /* CS9: VME Short I/O Access Range */
 262 #define CFG_VMESIOAR_BASE       0xFD000000
 263 #define CFG_VMESIOAR_SIZE       0x01000000
 264
 265 /*-----------------------------------------------------------------------
 266  * Hard Reset Configuration Words
 267  *
 268  * if you change bits in the HRCW, you must also change the CFG_*
 269  * defines for the various registers affected by the HRCW e.g. changing
 270  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 271  */
 272 #if defined(CONFIG_BOOT_ROM)
 273 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 274                                  HRCW_BPS01 | HRCW_CS10PC01)
 275 #else
 276 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 277 #endif
 278
 279 /* no slaves so just fill with zeros */
 280 #define CFG_HRCW_SLAVE1         0
 281 #define CFG_HRCW_SLAVE2         0
 282 #define CFG_HRCW_SLAVE3         0
 283 #define CFG_HRCW_SLAVE4         0
 284 #define CFG_HRCW_SLAVE5         0
 285 #define CFG_HRCW_SLAVE6         0
 286 #define CFG_HRCW_SLAVE7         0
 287
 288 /*-----------------------------------------------------------------------
 289  * Internal Memory Mapped Register
 290  */
 291 #define CFG_IMMR                0xF0000000
 292
 293 /*-----------------------------------------------------------------------
 294  * Definitions for initial stack pointer and data area (in DPRAM)
 295  */
 296 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 297 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 298 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 299 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 300 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 301
 302 /*-----------------------------------------------------------------------
 303  * Start addresses for the final memory configuration
 304  * (Set up by the startup code)
 305  * Please note that CFG_SDRAM_BASE _must_ start at 0
 306  *
 307  * 60x SDRAM is mapped at CFG_SDRAM_BASE.
 308  */
 309 #define CFG_SDRAM_BASE          0x00000000
 310 #define CFG_SDRAM_MAX_SIZE      0x08000000      /* max. 128 MB          */
 311 #define CFG_MONITOR_BASE        TEXT_BASE
 312 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 313 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 314
 315 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 316 # define CFG_RAMBOOT
 317 #endif
 318
 319 #if 0
 320 /* environment is in Flash */
 321 #define CFG_ENV_IS_IN_FLASH     1
 322 #ifdef CONFIG_BOOT_ROM
 323 # define CFG_ENV_ADDR           (CFG_FLASH_BASE+0x70000)
 324 # define CFG_ENV_SIZE           0x10000
 325 # define CFG_ENV_SECT_SIZE      0x10000
 326 #endif
 327 #else
 328 /* environment is in EEPROM */
 329 #define CFG_ENV_IS_IN_EEPROM    1
 330 #define CFG_I2C_EEPROM_ADDR     0x58    /* EEPROM X24C16                */
 331 #define CFG_I2C_EEPROM_ADDR_LEN 1
 332 /* mask of address bits that overflow into the "EEPROM chip address"    */
 333 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 334 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 335 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
 336 #define CFG_ENV_OFFSET          512
 337 #define CFG_ENV_SIZE            (2048 - 512)
 338 #endif
 339
 340 /*
 341  * Internal Definitions
 342  *
 343  * Boot Flags
 344  */
 345 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 346 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 347
 348
 349 /*-----------------------------------------------------------------------
 350  * Cache Configuration
 351  */
 352 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 353 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 354 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 355 #endif
 356
 357 /*-----------------------------------------------------------------------
 358  * HIDx - Hardware Implementation-dependent Registers                    2-11
 359  *-----------------------------------------------------------------------
 360  * HID0 also contains cache control - initially enable both caches and
 361  * invalidate contents, then the final state leaves only the instruction
 362  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 363  * but Soft reset does not.
 364  *
 365  * HID1 has only read-only information - nothing to set.
 366  */
 367 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
 368                          HID0_DCI|HID0_IFEM|HID0_ABE)
 369 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 370 #define CFG_HID2        0
 371
 372 /*-----------------------------------------------------------------------
 373  * RMR - Reset Mode Register                                     5-5
 374  *-----------------------------------------------------------------------
 375  * turn on Checkstop Reset Enable
 376  */
 377 #define CFG_RMR         RMR_CSRE
 378
 379 /*-----------------------------------------------------------------------
 380  * BCR - Bus Configuration                                       4-25
 381  *-----------------------------------------------------------------------
 382  */
 383 #define BCR_APD01       0x10000000
 384 #define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 385
 386 /*-----------------------------------------------------------------------
 387  * SIUMCR - SIU Module Configuration                             4-31
 388  *-----------------------------------------------------------------------
 389  */
 390 #define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 391                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 392
 393 /*-----------------------------------------------------------------------
 394  * SYPCR - System Protection Control                             4-35
 395  * SYPCR can only be written once after reset!
 396  *-----------------------------------------------------------------------
 397  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 398  */
 399 #if defined(CONFIG_WATCHDOG)
 400 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 401                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 402 #else
 403 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 404                          SYPCR_SWRI|SYPCR_SWP)
 405 #endif /* CONFIG_WATCHDOG */
 406
 407 /*-----------------------------------------------------------------------
 408  * TMCNTSC - Time Counter Status and Control                     4-40
 409  *-----------------------------------------------------------------------
 410  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 411  * and enable Time Counter
 412  */
 413 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 414
 415 /*-----------------------------------------------------------------------
 416  * PISCR - Periodic Interrupt Status and Control                 4-42
 417  *-----------------------------------------------------------------------
 418  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 419  * Periodic timer
 420  */
 421 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 422
 423 /*-----------------------------------------------------------------------
 424  * SCCR - System Clock Control                                   9-8
 425  *-----------------------------------------------------------------------
 426  * Ensure DFBRG is Divide by 16
 427  */
 428 #define CFG_SCCR        SCCR_DFBRG01
 429
 430 /*-----------------------------------------------------------------------
 431  * RCCR - RISC Controller Configuration                         13-7
 432  *-----------------------------------------------------------------------
 433  */
 434 #define CFG_RCCR        0
 435
 436 #define CFG_MIN_AM_MASK 0xC0000000
 437 /*-----------------------------------------------------------------------
 438  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 439  *-----------------------------------------------------------------------
 440  */
 441 #define CFG_MPTPR       0x1F00
 442
 443 /*-----------------------------------------------------------------------
 444  * PSRT - Refresh Timer Register                                10-16
 445  *-----------------------------------------------------------------------
 446  */
 447 #define CFG_PSRT        0x0f
 448
 449 /*-----------------------------------------------------------------------
 450  * PSRT - SDRAM Mode Register                                   10-10
 451  *-----------------------------------------------------------------------
 452  */
 453
 454         /* SDRAM initialization values for 8-column chips
 455          */
 456 #define CFG_OR2_8COL    (CFG_MIN_AM_MASK                |\
 457                          ORxS_BPD_4                     |\
 458                          ORxS_ROWST_PBI0_A9             |\
 459                          ORxS_NUMR_12)
 460
 461 #define CFG_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
 462                          PSDMR_BSMA_A14_A16             |\
 463                          PSDMR_SDA10_PBI0_A10           |\
 464                          PSDMR_RFRC_7_CLK               |\
 465                          PSDMR_PRETOACT_2W              |\
 466                          PSDMR_ACTTORW_1W               |\
 467                          PSDMR_LDOTOPRE_1C              |\
 468                          PSDMR_WRC_1C                   |\
 469                          PSDMR_CL_2)
 470
 471         /* SDRAM initialization values for 9-column chips
 472          */
 473 #define CFG_OR2_9COL    (CFG_MIN_AM_MASK                |\
 474                          ORxS_BPD_4                     |\
 475                          ORxS_ROWST_PBI0_A7             |\
 476                          ORxS_NUMR_13)
 477
 478 #define CFG_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
 479                          PSDMR_BSMA_A13_A15             |\
 480                          PSDMR_SDA10_PBI0_A9            |\
 481                          PSDMR_RFRC_7_CLK               |\
 482                          PSDMR_PRETOACT_2W              |\
 483                          PSDMR_ACTTORW_1W               |\
 484                          PSDMR_LDOTOPRE_1C              |\
 485                          PSDMR_WRC_1C                   |\
 486                          PSDMR_CL_2)
 487
 488 /*
 489  * Init Memory Controller:
 490  *
 491  * Bank Bus     Machine PortSz  Device
 492  * ---- ---     ------- ------  ------
 493  *  0   60x     GPCM    8  bit  Boot ROM
 494  *  1   60x     GPCM    64 bit  FLASH
 495  *  2   60x     SDRAM   64 bit  SDRAM
 496  *
 497  */
 498
 499 #define CFG_MRS_OFFS    0x00000000
 500
 501 #ifdef CONFIG_BOOT_ROM
 502 /* Bank 0 - Boot ROM
 503  */
 504 #define CFG_BR0_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
 505                          BRx_PS_8                       |\
 506                          BRx_MS_GPCM_P                  |\
 507                          BRx_V)
 508
 509 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
 510                          ORxG_CSNT                      |\
 511                          ORxG_ACS_DIV1                  |\
 512                          ORxG_SCY_3_CLK                 |\
 513                          ORxU_EHTR_8IDLE)
 514
 515 /* Bank 1 - FLASH
 516  */
 517 #define CFG_BR1_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 518                          BRx_PS_64                      |\
 519                          BRx_MS_GPCM_P                  |\
 520                          BRx_V)
 521
 522 #define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
 523                          ORxG_CSNT                      |\
 524                          ORxG_ACS_DIV1                  |\
 525                          ORxG_SCY_3_CLK                 |\
 526                          ORxU_EHTR_8IDLE)
 527
 528 #else /* CONFIG_BOOT_ROM */
 529 /* Bank 0 - FLASH
 530  */
 531 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 532                          BRx_PS_64                      |\
 533                          BRx_MS_GPCM_P                  |\
 534                          BRx_V)
 535
 536 #define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
 537                          ORxG_CSNT                      |\
 538                          ORxG_ACS_DIV1                  |\
 539                          ORxG_SCY_3_CLK                 |\
 540                          ORxU_EHTR_8IDLE)
 541
 542 /* Bank 1 - Boot ROM
 543  */
 544 #define CFG_BR1_PRELIM  ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
 545                          BRx_PS_8                       |\
 546                          BRx_MS_GPCM_P                  |\
 547                          BRx_V)
 548
 549 #define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_BOOTROM_SIZE)   |\
 550                          ORxG_CSNT                      |\
 551                          ORxG_ACS_DIV1                  |\
 552                          ORxG_SCY_3_CLK                 |\
 553                          ORxU_EHTR_8IDLE)
 554
 555 #endif /* CONFIG_BOOT_ROM */
 556
 557
 558 /* Bank 2 - 60x bus SDRAM
 559  */
 560 #ifndef CFG_RAMBOOT
 561 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 562                          BRx_PS_64                      |\
 563                          BRx_MS_SDRAM_P                 |\
 564                          BRx_V)
 565
 566 #define CFG_OR2_PRELIM   CFG_OR2_9COL
 567
 568 #define CFG_PSDMR        CFG_PSDMR_9COL
 569 #endif /* CFG_RAMBOOT */
 570
 571 /* Bank 3 - Dual Ported SRAM
 572  */
 573 #define CFG_BR3_PRELIM  ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
 574                          BRx_PS_16                      |\
 575                          BRx_MS_GPCM_P                  |\
 576                          BRx_V)
 577
 578 #define CFG_OR3_PRELIM  (P2SZ_TO_AM(CFG_DPSRAM_SIZE)    |\
 579                          ORxG_CSNT                      |\
 580                          ORxG_ACS_DIV1                  |\
 581                          ORxG_SCY_5_CLK                 |\
 582                          ORxG_SETA)
 583
 584 /* Bank 4 - DiskOnChip
 585  */
 586 #define CFG_BR4_PRELIM  ((CFG_DOC_BASE & BRx_BA_MSK)    |\
 587                          BRx_PS_8                       |\
 588                          BRx_MS_GPCM_P                  |\
 589                          BRx_V)
 590
 591 #define CFG_OR4_PRELIM  (P2SZ_TO_AM(CFG_DOC_SIZE)       |\
 592                          ORxG_ACS_DIV2                  |\
 593                          ORxG_SCY_5_CLK                 |\
 594                          ORxU_EHTR_8IDLE)
 595
 596 /* Bank 5 - FDC37C78 controller
 597  */
 598 #define CFG_BR5_PRELIM  ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
 599                          BRx_PS_8                         |\
 600                          BRx_MS_GPCM_P                    |\
 601                          BRx_V)
 602
 603 #define CFG_OR5_PRELIM  (P2SZ_TO_AM(CFG_FDC37C78_SIZE)    |\
 604                          ORxG_ACS_DIV2                    |\
 605                          ORxG_SCY_8_CLK                   |\
 606                          ORxU_EHTR_8IDLE)
 607
 608 /* Bank 6 - Board control registers
 609  */
 610 #define CFG_BR6_PRELIM  ((CFG_BCRS_BASE & BRx_BA_MSK)   |\
 611                          BRx_PS_8                       |\
 612                          BRx_MS_GPCM_P                  |\
 613                          BRx_V)
 614
 615 #define CFG_OR6_PRELIM  (P2SZ_TO_AM(CFG_BCRS_SIZE)      |\
 616                          ORxG_CSNT                      |\
 617                          ORxG_SCY_5_CLK)
 618
 619 /* Bank 7 - VME Extended Access Range
 620  */
 621 #define CFG_BR7_PRELIM  ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
 622                          BRx_PS_32                      |\
 623                          BRx_MS_GPCM_P                  |\
 624                          BRx_V)
 625
 626 #define CFG_OR7_PRELIM  (P2SZ_TO_AM(CFG_VMEEAR_SIZE)    |\
 627                          ORxG_CSNT                      |\
 628                          ORxG_ACS_DIV1                  |\
 629                          ORxG_SCY_5_CLK                 |\
 630                          ORxG_SETA)
 631
 632 /* Bank 8 - VME Standard Access Range
 633  */
 634 #define CFG_BR8_PRELIM  ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
 635                          BRx_PS_16                      |\
 636                          BRx_MS_GPCM_P                  |\
 637                          BRx_V)
 638
 639 #define CFG_OR8_PRELIM  (P2SZ_TO_AM(CFG_VMESAR_SIZE)    |\
 640                          ORxG_CSNT                      |\
 641                          ORxG_ACS_DIV1                  |\
 642                          ORxG_SCY_5_CLK                 |\
 643                          ORxG_SETA)
 644
 645 /* Bank 9 - VME Short I/O Access Range
 646  */
 647 #define CFG_BR9_PRELIM  ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
 648                          BRx_PS_16                        |\
 649                          BRx_MS_GPCM_P                    |\
 650                          BRx_V)
 651
 652 #define CFG_OR9_PRELIM  (P2SZ_TO_AM(CFG_VMESIOAR_SIZE)    |\
 653                          ORxG_CSNT                        |\
 654                          ORxG_ACS_DIV1                    |\
 655                          ORxG_SCY_5_CLK                   |\
 656                          ORxG_SETA)
 657
 658 #endif  /* __CONFIG_H */