include/configs/CPU87.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  37 #define CONFIG_CPU87            1       /* ...on a CPU87 board  */
  38 #define CONFIG_PCI
  39 #define CONFIG_CPM2             1       /* Has a CPM2 */
  40
  41 #ifdef CONFIG_BOOT_ROM
  42 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  43 #else
  44 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  45 #endif
  46
  47 /*
  48  * select serial console configuration
  49  *
  50  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  51  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  52  * for SCC).
  53  *
  54  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  55  * defined elsewhere (for example, on the cogent platform, there are serial
  56  * ports on the motherboard which are used for the serial console - see
  57  * cogent/cma101/serial.[ch]).
  58  */
  59 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  60 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  61 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  62 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  63
  64 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  65 #define CONFIG_BAUDRATE         230400
  66 #else
  67 #define CONFIG_BAUDRATE         9600
  68 #endif
  69
  70 /*
  71  * select ethernet configuration
  72  *
  73  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  74  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  75  * for FCC)
  76  *
  77  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  78  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  79  */
  80 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  81 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  82 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  83 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  84
  85 #define CONFIG_HAS_ETH1         1
  86 #define CONFIG_HAS_ETH2         1
  87
  88 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  89
  90 /*
  91  * - Rx-CLK is CLK11
  92  * - Tx-CLK is CLK12
  93  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  94  * - Enable Full Duplex in FSMR
  95  */
  96 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  97 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  98 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  99 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 100
 101 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 102
 103 /*
 104  * - Rx-CLK is CLK13
 105  * - Tx-CLK is CLK14
 106  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 107  * - Enable Full Duplex in FSMR
 108  */
 109 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 110 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 111 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 112 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 113
 114 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 115
 116 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 117 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 118
 119 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 120
 121 #define CONFIG_PREBOOT                                                          \
 122         "echo; "                                                                \
 123         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 124         "echo"
 125
 126 #undef  CONFIG_BOOTARGS
 127 #define CONFIG_BOOTCOMMAND                                                      \
 128         "bootp; "                                                               \
 129         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 130         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 131         "bootm"
 132
 133 /*-----------------------------------------------------------------------
 134  * I2C/EEPROM/RTC configuration
 135  */
 136 #define CONFIG_SOFT_I2C                 /* Software I2C support enabled */
 137
 138 # define CONFIG_SYS_I2C_SPEED           50000
 139 # define CONFIG_SYS_I2C_SLAVE           0xFE
 140 /*
 141  * Software (bit-bang) I2C driver configuration
 142  */
 143 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 144 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 145 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 146 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 147 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 148                         else    iop->pdat &= ~0x00010000
 149 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 150                         else    iop->pdat &= ~0x00020000
 151 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 152
 153 #define CONFIG_RTC_PCF8563
 154 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 155
 156 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 157
 158 /*-----------------------------------------------------------------------
 159  * Disk-On-Chip configuration
 160  */
 161
 162 #define CONFIG_SYS_MAX_DOC_DEVICE       1       /* Max number of DOC devices    */
 163
 164 #define CONFIG_SYS_DOC_SUPPORT_2000
 165 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 166
 167 /*-----------------------------------------------------------------------
 168  * Miscellaneous configuration options
 169  */
 170
 171 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 172 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 173
 174 /*
 175  * BOOTP options
 176  */
 177 #define CONFIG_BOOTP_SUBNETMASK
 178 #define CONFIG_BOOTP_GATEWAY
 179 #define CONFIG_BOOTP_HOSTNAME
 180 #define CONFIG_BOOTP_BOOTPATH
 181 #define CONFIG_BOOTP_BOOTFILESIZE
 182
 183
 184 /*
 185  * Command line configuration.
 186  */
 187 #include <config_cmd_default.h>
 188
 189 #define CONFIG_CMD_BEDBUG
 190 #define CONFIG_CMD_DATE
 191 #define CONFIG_CMD_EEPROM
 192 #define CONFIG_CMD_I2C
 193
 194 #ifdef CONFIG_PCI
 195     #define CONFIG_CMD_PCI
 196 #endif
 197
 198 /*
 199  * Miscellaneous configurable options
 200  */
 201 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 202 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 203 #if defined(CONFIG_CMD_KGDB)
 204 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 205 #else
 206 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 207 #endif
 208 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 209 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 210 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 211
 212 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 213 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
 214
 215 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 216
 217 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 218
 219 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 220
 221 #define CONFIG_LOOPW
 222
 223 /*
 224  * For booting Linux, the board info and command line data
 225  * have to be in the first 8 MB of memory, since this is
 226  * the maximum mapped by the Linux kernel during initialization.
 227  */
 228 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 229
 230 /*-----------------------------------------------------------------------
 231  * Flash configuration
 232  */
 233
 234 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 235 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 236 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 237 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 238
 239 /*-----------------------------------------------------------------------
 240  * FLASH organization
 241  */
 242 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 243 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 244
 245 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 246 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 247
 248 /*-----------------------------------------------------------------------
 249  * Other areas to be mapped
 250  */
 251
 252 /* CS3: Dual ported SRAM */
 253 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 254 #define CONFIG_SYS_DPSRAM_SIZE          0x00100000
 255
 256 /* CS4: DiskOnChip */
 257 #define CONFIG_SYS_DOC_BASE             0xF4000000
 258 #define CONFIG_SYS_DOC_SIZE             0x00100000
 259
 260 /* CS5: FDC37C78 controller */
 261 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 262 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 263
 264 /* CS6: Board configuration registers */
 265 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 266 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 267
 268 /* CS7: VME Extended Access Range */
 269 #define CONFIG_SYS_VMEEAR_BASE          0x60000000
 270 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 271
 272 /* CS8: VME Standard Access Range */
 273 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 274 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 275
 276 /* CS9: VME Short I/O Access Range */
 277 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 278 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 279
 280 /*-----------------------------------------------------------------------
 281  * Hard Reset Configuration Words
 282  *
 283  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 284  * defines for the various registers affected by the HRCW e.g. changing
 285  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 286  */
 287 #if defined(CONFIG_BOOT_ROM)
 288 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 289                                  HRCW_BPS01 | HRCW_CS10PC01)
 290 #else
 291 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 292 #endif
 293
 294 /* no slaves so just fill with zeros */
 295 #define CONFIG_SYS_HRCW_SLAVE1          0
 296 #define CONFIG_SYS_HRCW_SLAVE2          0
 297 #define CONFIG_SYS_HRCW_SLAVE3          0
 298 #define CONFIG_SYS_HRCW_SLAVE4          0
 299 #define CONFIG_SYS_HRCW_SLAVE5          0
 300 #define CONFIG_SYS_HRCW_SLAVE6          0
 301 #define CONFIG_SYS_HRCW_SLAVE7          0
 302
 303 /*-----------------------------------------------------------------------
 304  * Internal Memory Mapped Register
 305  */
 306 #define CONFIG_SYS_IMMR         0xF0000000
 307
 308 /*-----------------------------------------------------------------------
 309  * Definitions for initial stack pointer and data area (in DPRAM)
 310  */
 311 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 312 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 313 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 314 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 315
 316 /*-----------------------------------------------------------------------
 317  * Start addresses for the final memory configuration
 318  * (Set up by the startup code)
 319  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 320  *
 321  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 322  */
 323 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 324 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 325 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 326 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 327 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 328
 329 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 330 # define CONFIG_SYS_RAMBOOT
 331 #endif
 332
 333 #ifdef  CONFIG_PCI
 334 #define CONFIG_PCI_PNP
 335 #define CONFIG_EEPRO100
 336 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 337 #endif
 338
 339 #if 0
 340 /* environment is in Flash */
 341 #define CONFIG_ENV_IS_IN_FLASH  1
 342 #ifdef CONFIG_BOOT_ROM
 343 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 344 # define CONFIG_ENV_SIZE                0x10000
 345 # define CONFIG_ENV_SECT_SIZE   0x10000
 346 #endif
 347 #else
 348 /* environment is in EEPROM */
 349 #define CONFIG_ENV_IS_IN_EEPROM 1
 350 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 351 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 352 /* mask of address bits that overflow into the "EEPROM chip address"    */
 353 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 354 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 355 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 356 #define CONFIG_ENV_OFFSET               512
 357 #define CONFIG_ENV_SIZE         (2048 - 512)
 358 #endif
 359
 360 /*-----------------------------------------------------------------------
 361  * Cache Configuration
 362  */
 363 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 364 #if defined(CONFIG_CMD_KGDB)
 365 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 366 #endif
 367
 368 /*-----------------------------------------------------------------------
 369  * HIDx - Hardware Implementation-dependent Registers                    2-11
 370  *-----------------------------------------------------------------------
 371  * HID0 also contains cache control - initially enable both caches and
 372  * invalidate contents, then the final state leaves only the instruction
 373  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 374  * but Soft reset does not.
 375  *
 376  * HID1 has only read-only information - nothing to set.
 377  */
 378 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|\
 379                          HID0_DCI|HID0_IFEM|HID0_ABE)
 380 #define CONFIG_SYS_HID0_FINAL   (HID0_IFEM|HID0_ABE)
 381 #define CONFIG_SYS_HID2 0
 382
 383 /*-----------------------------------------------------------------------
 384  * RMR - Reset Mode Register                                     5-5
 385  *-----------------------------------------------------------------------
 386  * turn on Checkstop Reset Enable
 387  */
 388 #define CONFIG_SYS_RMR          RMR_CSRE
 389
 390 /*-----------------------------------------------------------------------
 391  * BCR - Bus Configuration                                       4-25
 392  *-----------------------------------------------------------------------
 393  */
 394 #define BCR_APD01       0x10000000
 395 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 396
 397 /*-----------------------------------------------------------------------
 398  * SIUMCR - SIU Module Configuration                             4-31
 399  *-----------------------------------------------------------------------
 400  */
 401 #define CONFIG_SYS_SIUMCR       (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 402                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 403
 404 /*-----------------------------------------------------------------------
 405  * SYPCR - System Protection Control                             4-35
 406  * SYPCR can only be written once after reset!
 407  *-----------------------------------------------------------------------
 408  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 409  */
 410 #if defined(CONFIG_WATCHDOG)
 411 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 412                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 413 #else
 414 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 415                          SYPCR_SWRI|SYPCR_SWP)
 416 #endif /* CONFIG_WATCHDOG */
 417
 418 /*-----------------------------------------------------------------------
 419  * TMCNTSC - Time Counter Status and Control                     4-40
 420  *-----------------------------------------------------------------------
 421  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 422  * and enable Time Counter
 423  */
 424 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 425
 426 /*-----------------------------------------------------------------------
 427  * PISCR - Periodic Interrupt Status and Control                 4-42
 428  *-----------------------------------------------------------------------
 429  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 430  * Periodic timer
 431  */
 432 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 433
 434 /*-----------------------------------------------------------------------
 435  * SCCR - System Clock Control                                   9-8
 436  *-----------------------------------------------------------------------
 437  * Ensure DFBRG is Divide by 16
 438  */
 439 #define CONFIG_SYS_SCCR SCCR_DFBRG01
 440
 441 /*-----------------------------------------------------------------------
 442  * RCCR - RISC Controller Configuration                         13-7
 443  *-----------------------------------------------------------------------
 444  */
 445 #define CONFIG_SYS_RCCR 0
 446
 447 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 448
 449 /*
 450  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
 451  * refresh rate = 7.68 uS (100 MHz Bus Clock)
 452  */
 453
 454 /*-----------------------------------------------------------------------
 455  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 456  *-----------------------------------------------------------------------
 457  */
 458 #define CONFIG_SYS_MPTPR        0x2000
 459
 460 /*-----------------------------------------------------------------------
 461  * PSRT - Refresh Timer Register                                10-16
 462  *-----------------------------------------------------------------------
 463  */
 464 #define CONFIG_SYS_PSRT 0x16
 465
 466 /*-----------------------------------------------------------------------
 467  * PSRT - SDRAM Mode Register                                   10-10
 468  *-----------------------------------------------------------------------
 469  */
 470
 471         /* SDRAM initialization values for 8-column chips
 472          */
 473 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 474                          ORxS_BPD_4                     |\
 475                          ORxS_ROWST_PBI0_A9             |\
 476                          ORxS_NUMR_12)
 477
 478 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 479                          PSDMR_BSMA_A14_A16             |\
 480                          PSDMR_SDA10_PBI0_A10           |\
 481                          PSDMR_RFRC_7_CLK               |\
 482                          PSDMR_PRETOACT_2W              |\
 483                          PSDMR_ACTTORW_2W               |\
 484                          PSDMR_LDOTOPRE_1C              |\
 485                          PSDMR_WRC_1C                   |\
 486                          PSDMR_CL_2)
 487
 488         /* SDRAM initialization values for 9-column chips
 489          */
 490 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 491                          ORxS_BPD_4                     |\
 492                          ORxS_ROWST_PBI0_A7             |\
 493                          ORxS_NUMR_13)
 494
 495 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 496                          PSDMR_BSMA_A13_A15             |\
 497                          PSDMR_SDA10_PBI0_A9            |\
 498                          PSDMR_RFRC_7_CLK               |\
 499                          PSDMR_PRETOACT_2W              |\
 500                          PSDMR_ACTTORW_2W               |\
 501                          PSDMR_LDOTOPRE_1C              |\
 502                          PSDMR_WRC_1C                   |\
 503                          PSDMR_CL_2)
 504
 505         /* SDRAM initialization values for 10-column chips
 506          */
 507 #define CONFIG_SYS_OR2_10COL    (CONFIG_SYS_MIN_AM_MASK         |\
 508                          ORxS_BPD_4                     |\
 509                          ORxS_ROWST_PBI1_A4             |\
 510                          ORxS_NUMR_13)
 511
 512 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 513                          PSDMR_SDAM_A17_IS_A5           |\
 514                          PSDMR_BSMA_A13_A15             |\
 515                          PSDMR_SDA10_PBI1_A6            |\
 516                          PSDMR_RFRC_7_CLK               |\
 517                          PSDMR_PRETOACT_2W              |\
 518                          PSDMR_ACTTORW_2W               |\
 519                          PSDMR_LDOTOPRE_1C              |\
 520                          PSDMR_WRC_1C                   |\
 521                          PSDMR_CL_2)
 522
 523 /*
 524  * Init Memory Controller:
 525  *
 526  * Bank Bus     Machine PortSz  Device
 527  * ---- ---     ------- ------  ------
 528  *  0   60x     GPCM    8  bit  Boot ROM
 529  *  1   60x     GPCM    64 bit  FLASH
 530  *  2   60x     SDRAM   64 bit  SDRAM
 531  *
 532  */
 533
 534 #define CONFIG_SYS_MRS_OFFS     0x00000000
 535
 536 #ifdef CONFIG_BOOT_ROM
 537 /* Bank 0 - Boot ROM
 538  */
 539 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 540                          BRx_PS_8                       |\
 541                          BRx_MS_GPCM_P                  |\
 542                          BRx_V)
 543
 544 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 545                          ORxG_CSNT                      |\
 546                          ORxG_ACS_DIV1                  |\
 547                          ORxG_SCY_5_CLK                 |\
 548                          ORxU_EHTR_8IDLE)
 549
 550 /* Bank 1 - FLASH
 551  */
 552 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 553                          BRx_PS_64                      |\
 554                          BRx_MS_GPCM_P                  |\
 555                          BRx_V)
 556
 557 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 558                          ORxG_CSNT                      |\
 559                          ORxG_ACS_DIV1                  |\
 560                          ORxG_SCY_5_CLK                 |\
 561                          ORxU_EHTR_8IDLE)
 562
 563 #else /* CONFIG_BOOT_ROM */
 564 /* Bank 0 - FLASH
 565  */
 566 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 567                          BRx_PS_64                      |\
 568                          BRx_MS_GPCM_P                  |\
 569                          BRx_V)
 570
 571 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 572                          ORxG_CSNT                      |\
 573                          ORxG_ACS_DIV1                  |\
 574                          ORxG_SCY_5_CLK                 |\
 575                          ORxU_EHTR_8IDLE)
 576
 577 /* Bank 1 - Boot ROM
 578  */
 579 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 580                          BRx_PS_8                       |\
 581                          BRx_MS_GPCM_P                  |\
 582                          BRx_V)
 583
 584 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 585                          ORxG_CSNT                      |\
 586                          ORxG_ACS_DIV1                  |\
 587                          ORxG_SCY_5_CLK                 |\
 588                          ORxU_EHTR_8IDLE)
 589
 590 #endif /* CONFIG_BOOT_ROM */
 591
 592
 593 /* Bank 2 - 60x bus SDRAM
 594  */
 595 #ifndef CONFIG_SYS_RAMBOOT
 596 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
 597                          BRx_PS_64                      |\
 598                          BRx_MS_SDRAM_P                 |\
 599                          BRx_V)
 600
 601 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
 602
 603 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
 604 #endif /* CONFIG_SYS_RAMBOOT */
 605
 606 /* Bank 3 - Dual Ported SRAM
 607  */
 608 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 609                          BRx_PS_16                      |\
 610                          BRx_MS_GPCM_P                  |\
 611                          BRx_V)
 612
 613 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)     |\
 614                          ORxG_CSNT                      |\
 615                          ORxG_ACS_DIV1                  |\
 616                          ORxG_SCY_7_CLK                 |\
 617                          ORxG_SETA)
 618
 619 /* Bank 4 - DiskOnChip
 620  */
 621 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 622                          BRx_PS_8                       |\
 623                          BRx_MS_GPCM_P                  |\
 624                          BRx_V)
 625
 626 #define CONFIG_SYS_OR4_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 627                          ORxG_CSNT                      |\
 628                          ORxG_ACS_DIV2                  |\
 629                          ORxG_SCY_9_CLK                 |\
 630                          ORxU_EHTR_8IDLE)
 631
 632 /* Bank 5 - FDC37C78 controller
 633  */
 634 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 635                          BRx_PS_8                         |\
 636                          BRx_MS_GPCM_P                    |\
 637                          BRx_V)
 638
 639 #define CONFIG_SYS_OR5_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)     |\
 640                          ORxG_ACS_DIV2                    |\
 641                          ORxG_SCY_10_CLK                  |\
 642                          ORxU_EHTR_8IDLE)
 643
 644 /* Bank 6 - Board control registers
 645  */
 646 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)    |\
 647                          BRx_PS_8                       |\
 648                          BRx_MS_GPCM_P                  |\
 649                          BRx_V)
 650
 651 #define CONFIG_SYS_OR6_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)       |\
 652                          ORxG_CSNT                      |\
 653                          ORxG_SCY_7_CLK)
 654
 655 /* Bank 7 - VME Extended Access Range
 656  */
 657 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 658                          BRx_PS_32                      |\
 659                          BRx_MS_GPCM_P                  |\
 660                          BRx_V)
 661
 662 #define CONFIG_SYS_OR7_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)     |\
 663                          ORxG_CSNT                      |\
 664                          ORxG_ACS_DIV1                  |\
 665                          ORxG_SCY_7_CLK                 |\
 666                          ORxG_SETA)
 667
 668 /* Bank 8 - VME Standard Access Range
 669  */
 670 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 671                          BRx_PS_16                      |\
 672                          BRx_MS_GPCM_P                  |\
 673                          BRx_V)
 674
 675 #define CONFIG_SYS_OR8_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)     |\
 676                          ORxG_CSNT                      |\
 677                          ORxG_ACS_DIV1                  |\
 678                          ORxG_SCY_7_CLK                 |\
 679                          ORxG_SETA)
 680
 681 /* Bank 9 - VME Short I/O Access Range
 682  */
 683 #define CONFIG_SYS_BR9_PRELIM   ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 684                          BRx_PS_16                        |\
 685                          BRx_MS_GPCM_P                    |\
 686                          BRx_V)
 687
 688 #define CONFIG_SYS_OR9_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)     |\
 689                          ORxG_CSNT                        |\
 690                          ORxG_ACS_DIV1                    |\
 691                          ORxG_SCY_7_CLK                   |\
 692                          ORxG_SETA)
 693
 694 #endif  /* __CONFIG_H */