include/configs/CPU87.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  21 #define CONFIG_CPU87            1       /* ...on a CPU87 board  */
  22 #define CONFIG_PCI
  23 #define CONFIG_CPM2             1       /* Has a CPM2 */
  24
  25 #ifdef CONFIG_BOOT_ROM
  26 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  27 #else
  28 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  29 #endif
  30
  31 /*
  32  * select serial console configuration
  33  *
  34  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  35  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  36  * for SCC).
  37  *
  38  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  39  * defined elsewhere (for example, on the cogent platform, there are serial
  40  * ports on the motherboard which are used for the serial console - see
  41  * cogent/cma101/serial.[ch]).
  42  */
  43 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  44 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  45 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  46 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  47
  48 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  49 #define CONFIG_BAUDRATE         230400
  50 #else
  51 #define CONFIG_BAUDRATE         9600
  52 #endif
  53
  54 /*
  55  * select ethernet configuration
  56  *
  57  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  58  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  59  * for FCC)
  60  *
  61  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  62  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  63  */
  64 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  65 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  66 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  67 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  68
  69 #define CONFIG_HAS_ETH1         1
  70 #define CONFIG_HAS_ETH2         1
  71
  72 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  73
  74 /*
  75  * - Rx-CLK is CLK11
  76  * - Tx-CLK is CLK12
  77  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  78  * - Enable Full Duplex in FSMR
  79  */
  80 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  81 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  82 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  83 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  84
  85 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  86
  87 /*
  88  * - Rx-CLK is CLK13
  89  * - Tx-CLK is CLK14
  90  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  91  * - Enable Full Duplex in FSMR
  92  */
  93 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  94 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  95 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  96 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  97
  98 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  99
 100 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 101 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 102
 103 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 104
 105 #define CONFIG_PREBOOT                                                          \
 106         "echo; "                                                                \
 107         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 108         "echo"
 109
 110 #undef  CONFIG_BOOTARGS
 111 #define CONFIG_BOOTCOMMAND                                                      \
 112         "bootp; "                                                               \
 113         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 114         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 115         "bootm"
 116
 117 /*-----------------------------------------------------------------------
 118  * I2C/EEPROM/RTC configuration
 119  */
 120 #define CONFIG_SYS_I2C
 121 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 122 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 123 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 124
 125 /*
 126  * Software (bit-bang) I2C driver configuration
 127  */
 128 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 129 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 130 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 131 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 132 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 133                         else    iop->pdat &= ~0x00010000
 134 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 135                         else    iop->pdat &= ~0x00020000
 136 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 137
 138 #define CONFIG_RTC_PCF8563
 139 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 140
 141 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 142
 143 /*-----------------------------------------------------------------------
 144  * Disk-On-Chip configuration
 145  */
 146
 147 #define CONFIG_SYS_MAX_DOC_DEVICE       1       /* Max number of DOC devices    */
 148
 149 #define CONFIG_SYS_DOC_SUPPORT_2000
 150 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 151
 152 /*-----------------------------------------------------------------------
 153  * Miscellaneous configuration options
 154  */
 155
 156 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 157 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 158
 159 /*
 160  * BOOTP options
 161  */
 162 #define CONFIG_BOOTP_SUBNETMASK
 163 #define CONFIG_BOOTP_GATEWAY
 164 #define CONFIG_BOOTP_HOSTNAME
 165 #define CONFIG_BOOTP_BOOTPATH
 166 #define CONFIG_BOOTP_BOOTFILESIZE
 167
 168
 169 /*
 170  * Command line configuration.
 171  */
 172 #include <config_cmd_default.h>
 173
 174 #define CONFIG_CMD_BEDBUG
 175 #define CONFIG_CMD_DATE
 176 #define CONFIG_CMD_EEPROM
 177 #define CONFIG_CMD_I2C
 178
 179 #ifdef CONFIG_PCI
 180 #define CONFIG_PCI_INDIRECT_BRIDGE
 181     #define CONFIG_CMD_PCI
 182 #endif
 183
 184 /*
 185  * Miscellaneous configurable options
 186  */
 187 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 188 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 189 #if defined(CONFIG_CMD_KGDB)
 190 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 191 #else
 192 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 193 #endif
 194 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 195 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 196 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 197
 198 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 199 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
 200
 201 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 202
 203 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 204
 205 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 206
 207 #define CONFIG_LOOPW
 208
 209 /*
 210  * For booting Linux, the board info and command line data
 211  * have to be in the first 8 MB of memory, since this is
 212  * the maximum mapped by the Linux kernel during initialization.
 213  */
 214 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 215
 216 /*-----------------------------------------------------------------------
 217  * Flash configuration
 218  */
 219
 220 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 221 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 222 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 223 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 224
 225 /*-----------------------------------------------------------------------
 226  * FLASH organization
 227  */
 228 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 230
 231 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 233
 234 /*-----------------------------------------------------------------------
 235  * Other areas to be mapped
 236  */
 237
 238 /* CS3: Dual ported SRAM */
 239 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 240 #define CONFIG_SYS_DPSRAM_SIZE          0x00100000
 241
 242 /* CS4: DiskOnChip */
 243 #define CONFIG_SYS_DOC_BASE             0xF4000000
 244 #define CONFIG_SYS_DOC_SIZE             0x00100000
 245
 246 /* CS5: FDC37C78 controller */
 247 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 248 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 249
 250 /* CS6: Board configuration registers */
 251 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 252 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 253
 254 /* CS7: VME Extended Access Range */
 255 #define CONFIG_SYS_VMEEAR_BASE          0x60000000
 256 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 257
 258 /* CS8: VME Standard Access Range */
 259 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 260 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 261
 262 /* CS9: VME Short I/O Access Range */
 263 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 264 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 265
 266 /*-----------------------------------------------------------------------
 267  * Hard Reset Configuration Words
 268  *
 269  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 270  * defines for the various registers affected by the HRCW e.g. changing
 271  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 272  */
 273 #if defined(CONFIG_BOOT_ROM)
 274 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 275                                  HRCW_BPS01 | HRCW_CS10PC01)
 276 #else
 277 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 278 #endif
 279
 280 /* no slaves so just fill with zeros */
 281 #define CONFIG_SYS_HRCW_SLAVE1          0
 282 #define CONFIG_SYS_HRCW_SLAVE2          0
 283 #define CONFIG_SYS_HRCW_SLAVE3          0
 284 #define CONFIG_SYS_HRCW_SLAVE4          0
 285 #define CONFIG_SYS_HRCW_SLAVE5          0
 286 #define CONFIG_SYS_HRCW_SLAVE6          0
 287 #define CONFIG_SYS_HRCW_SLAVE7          0
 288
 289 /*-----------------------------------------------------------------------
 290  * Internal Memory Mapped Register
 291  */
 292 #define CONFIG_SYS_IMMR         0xF0000000
 293
 294 /*-----------------------------------------------------------------------
 295  * Definitions for initial stack pointer and data area (in DPRAM)
 296  */
 297 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 298 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 299 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 300 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 301
 302 /*-----------------------------------------------------------------------
 303  * Start addresses for the final memory configuration
 304  * (Set up by the startup code)
 305  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 306  *
 307  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 308  */
 309 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 310 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 311 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 312 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 313 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 314
 315 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 316 # define CONFIG_SYS_RAMBOOT
 317 #endif
 318
 319 #ifdef  CONFIG_PCI
 320 #define CONFIG_PCI_PNP
 321 #define CONFIG_EEPRO100
 322 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 323 #endif
 324
 325 #if 0
 326 /* environment is in Flash */
 327 #define CONFIG_ENV_IS_IN_FLASH  1
 328 #ifdef CONFIG_BOOT_ROM
 329 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 330 # define CONFIG_ENV_SIZE                0x10000
 331 # define CONFIG_ENV_SECT_SIZE   0x10000
 332 #endif
 333 #else
 334 /* environment is in EEPROM */
 335 #define CONFIG_ENV_IS_IN_EEPROM 1
 336 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 337 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 338 /* mask of address bits that overflow into the "EEPROM chip address"    */
 339 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 340 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 341 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 342 #define CONFIG_ENV_OFFSET               512
 343 #define CONFIG_ENV_SIZE         (2048 - 512)
 344 #endif
 345
 346 /*-----------------------------------------------------------------------
 347  * Cache Configuration
 348  */
 349 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 350 #if defined(CONFIG_CMD_KGDB)
 351 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 352 #endif
 353
 354 /*-----------------------------------------------------------------------
 355  * HIDx - Hardware Implementation-dependent Registers                    2-11
 356  *-----------------------------------------------------------------------
 357  * HID0 also contains cache control - initially enable both caches and
 358  * invalidate contents, then the final state leaves only the instruction
 359  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 360  * but Soft reset does not.
 361  *
 362  * HID1 has only read-only information - nothing to set.
 363  */
 364 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|\
 365                          HID0_DCI|HID0_IFEM|HID0_ABE)
 366 #define CONFIG_SYS_HID0_FINAL   (HID0_IFEM|HID0_ABE)
 367 #define CONFIG_SYS_HID2 0
 368
 369 /*-----------------------------------------------------------------------
 370  * RMR - Reset Mode Register                                     5-5
 371  *-----------------------------------------------------------------------
 372  * turn on Checkstop Reset Enable
 373  */
 374 #define CONFIG_SYS_RMR          RMR_CSRE
 375
 376 /*-----------------------------------------------------------------------
 377  * BCR - Bus Configuration                                       4-25
 378  *-----------------------------------------------------------------------
 379  */
 380 #define BCR_APD01       0x10000000
 381 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 382
 383 /*-----------------------------------------------------------------------
 384  * SIUMCR - SIU Module Configuration                             4-31
 385  *-----------------------------------------------------------------------
 386  */
 387 #define CONFIG_SYS_SIUMCR       (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 388                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 389
 390 /*-----------------------------------------------------------------------
 391  * SYPCR - System Protection Control                             4-35
 392  * SYPCR can only be written once after reset!
 393  *-----------------------------------------------------------------------
 394  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 395  */
 396 #if defined(CONFIG_WATCHDOG)
 397 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 398                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 399 #else
 400 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 401                          SYPCR_SWRI|SYPCR_SWP)
 402 #endif /* CONFIG_WATCHDOG */
 403
 404 /*-----------------------------------------------------------------------
 405  * TMCNTSC - Time Counter Status and Control                     4-40
 406  *-----------------------------------------------------------------------
 407  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 408  * and enable Time Counter
 409  */
 410 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 411
 412 /*-----------------------------------------------------------------------
 413  * PISCR - Periodic Interrupt Status and Control                 4-42
 414  *-----------------------------------------------------------------------
 415  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 416  * Periodic timer
 417  */
 418 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 419
 420 /*-----------------------------------------------------------------------
 421  * SCCR - System Clock Control                                   9-8
 422  *-----------------------------------------------------------------------
 423  * Ensure DFBRG is Divide by 16
 424  */
 425 #define CONFIG_SYS_SCCR SCCR_DFBRG01
 426
 427 /*-----------------------------------------------------------------------
 428  * RCCR - RISC Controller Configuration                         13-7
 429  *-----------------------------------------------------------------------
 430  */
 431 #define CONFIG_SYS_RCCR 0
 432
 433 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 434
 435 /*
 436  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
 437  * refresh rate = 7.68 uS (100 MHz Bus Clock)
 438  */
 439
 440 /*-----------------------------------------------------------------------
 441  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 442  *-----------------------------------------------------------------------
 443  */
 444 #define CONFIG_SYS_MPTPR        0x2000
 445
 446 /*-----------------------------------------------------------------------
 447  * PSRT - Refresh Timer Register                                10-16
 448  *-----------------------------------------------------------------------
 449  */
 450 #define CONFIG_SYS_PSRT 0x16
 451
 452 /*-----------------------------------------------------------------------
 453  * PSRT - SDRAM Mode Register                                   10-10
 454  *-----------------------------------------------------------------------
 455  */
 456
 457         /* SDRAM initialization values for 8-column chips
 458          */
 459 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 460                          ORxS_BPD_4                     |\
 461                          ORxS_ROWST_PBI0_A9             |\
 462                          ORxS_NUMR_12)
 463
 464 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 465                          PSDMR_BSMA_A14_A16             |\
 466                          PSDMR_SDA10_PBI0_A10           |\
 467                          PSDMR_RFRC_7_CLK               |\
 468                          PSDMR_PRETOACT_2W              |\
 469                          PSDMR_ACTTORW_2W               |\
 470                          PSDMR_LDOTOPRE_1C              |\
 471                          PSDMR_WRC_1C                   |\
 472                          PSDMR_CL_2)
 473
 474         /* SDRAM initialization values for 9-column chips
 475          */
 476 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 477                          ORxS_BPD_4                     |\
 478                          ORxS_ROWST_PBI0_A7             |\
 479                          ORxS_NUMR_13)
 480
 481 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 482                          PSDMR_BSMA_A13_A15             |\
 483                          PSDMR_SDA10_PBI0_A9            |\
 484                          PSDMR_RFRC_7_CLK               |\
 485                          PSDMR_PRETOACT_2W              |\
 486                          PSDMR_ACTTORW_2W               |\
 487                          PSDMR_LDOTOPRE_1C              |\
 488                          PSDMR_WRC_1C                   |\
 489                          PSDMR_CL_2)
 490
 491         /* SDRAM initialization values for 10-column chips
 492          */
 493 #define CONFIG_SYS_OR2_10COL    (CONFIG_SYS_MIN_AM_MASK         |\
 494                          ORxS_BPD_4                     |\
 495                          ORxS_ROWST_PBI1_A4             |\
 496                          ORxS_NUMR_13)
 497
 498 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 499                          PSDMR_SDAM_A17_IS_A5           |\
 500                          PSDMR_BSMA_A13_A15             |\
 501                          PSDMR_SDA10_PBI1_A6            |\
 502                          PSDMR_RFRC_7_CLK               |\
 503                          PSDMR_PRETOACT_2W              |\
 504                          PSDMR_ACTTORW_2W               |\
 505                          PSDMR_LDOTOPRE_1C              |\
 506                          PSDMR_WRC_1C                   |\
 507                          PSDMR_CL_2)
 508
 509 /*
 510  * Init Memory Controller:
 511  *
 512  * Bank Bus     Machine PortSz  Device
 513  * ---- ---     ------- ------  ------
 514  *  0   60x     GPCM    8  bit  Boot ROM
 515  *  1   60x     GPCM    64 bit  FLASH
 516  *  2   60x     SDRAM   64 bit  SDRAM
 517  *
 518  */
 519
 520 #define CONFIG_SYS_MRS_OFFS     0x00000000
 521
 522 #ifdef CONFIG_BOOT_ROM
 523 /* Bank 0 - Boot ROM
 524  */
 525 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 526                          BRx_PS_8                       |\
 527                          BRx_MS_GPCM_P                  |\
 528                          BRx_V)
 529
 530 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 531                          ORxG_CSNT                      |\
 532                          ORxG_ACS_DIV1                  |\
 533                          ORxG_SCY_5_CLK                 |\
 534                          ORxU_EHTR_8IDLE)
 535
 536 /* Bank 1 - FLASH
 537  */
 538 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 539                          BRx_PS_64                      |\
 540                          BRx_MS_GPCM_P                  |\
 541                          BRx_V)
 542
 543 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 544                          ORxG_CSNT                      |\
 545                          ORxG_ACS_DIV1                  |\
 546                          ORxG_SCY_5_CLK                 |\
 547                          ORxU_EHTR_8IDLE)
 548
 549 #else /* CONFIG_BOOT_ROM */
 550 /* Bank 0 - FLASH
 551  */
 552 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 553                          BRx_PS_64                      |\
 554                          BRx_MS_GPCM_P                  |\
 555                          BRx_V)
 556
 557 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 558                          ORxG_CSNT                      |\
 559                          ORxG_ACS_DIV1                  |\
 560                          ORxG_SCY_5_CLK                 |\
 561                          ORxU_EHTR_8IDLE)
 562
 563 /* Bank 1 - Boot ROM
 564  */
 565 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 566                          BRx_PS_8                       |\
 567                          BRx_MS_GPCM_P                  |\
 568                          BRx_V)
 569
 570 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 571                          ORxG_CSNT                      |\
 572                          ORxG_ACS_DIV1                  |\
 573                          ORxG_SCY_5_CLK                 |\
 574                          ORxU_EHTR_8IDLE)
 575
 576 #endif /* CONFIG_BOOT_ROM */
 577
 578
 579 /* Bank 2 - 60x bus SDRAM
 580  */
 581 #ifndef CONFIG_SYS_RAMBOOT
 582 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
 583                          BRx_PS_64                      |\
 584                          BRx_MS_SDRAM_P                 |\
 585                          BRx_V)
 586
 587 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
 588
 589 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
 590 #endif /* CONFIG_SYS_RAMBOOT */
 591
 592 /* Bank 3 - Dual Ported SRAM
 593  */
 594 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 595                          BRx_PS_16                      |\
 596                          BRx_MS_GPCM_P                  |\
 597                          BRx_V)
 598
 599 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)     |\
 600                          ORxG_CSNT                      |\
 601                          ORxG_ACS_DIV1                  |\
 602                          ORxG_SCY_7_CLK                 |\
 603                          ORxG_SETA)
 604
 605 /* Bank 4 - DiskOnChip
 606  */
 607 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 608                          BRx_PS_8                       |\
 609                          BRx_MS_GPCM_P                  |\
 610                          BRx_V)
 611
 612 #define CONFIG_SYS_OR4_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 613                          ORxG_CSNT                      |\
 614                          ORxG_ACS_DIV2                  |\
 615                          ORxG_SCY_9_CLK                 |\
 616                          ORxU_EHTR_8IDLE)
 617
 618 /* Bank 5 - FDC37C78 controller
 619  */
 620 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 621                          BRx_PS_8                         |\
 622                          BRx_MS_GPCM_P                    |\
 623                          BRx_V)
 624
 625 #define CONFIG_SYS_OR5_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)     |\
 626                          ORxG_ACS_DIV2                    |\
 627                          ORxG_SCY_10_CLK                  |\
 628                          ORxU_EHTR_8IDLE)
 629
 630 /* Bank 6 - Board control registers
 631  */
 632 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)    |\
 633                          BRx_PS_8                       |\
 634                          BRx_MS_GPCM_P                  |\
 635                          BRx_V)
 636
 637 #define CONFIG_SYS_OR6_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)       |\
 638                          ORxG_CSNT                      |\
 639                          ORxG_SCY_7_CLK)
 640
 641 /* Bank 7 - VME Extended Access Range
 642  */
 643 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 644                          BRx_PS_32                      |\
 645                          BRx_MS_GPCM_P                  |\
 646                          BRx_V)
 647
 648 #define CONFIG_SYS_OR7_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)     |\
 649                          ORxG_CSNT                      |\
 650                          ORxG_ACS_DIV1                  |\
 651                          ORxG_SCY_7_CLK                 |\
 652                          ORxG_SETA)
 653
 654 /* Bank 8 - VME Standard Access Range
 655  */
 656 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 657                          BRx_PS_16                      |\
 658                          BRx_MS_GPCM_P                  |\
 659                          BRx_V)
 660
 661 #define CONFIG_SYS_OR8_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)     |\
 662                          ORxG_CSNT                      |\
 663                          ORxG_ACS_DIV1                  |\
 664                          ORxG_SCY_7_CLK                 |\
 665                          ORxG_SETA)
 666
 667 /* Bank 9 - VME Short I/O Access Range
 668  */
 669 #define CONFIG_SYS_BR9_PRELIM   ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 670                          BRx_PS_16                        |\
 671                          BRx_MS_GPCM_P                    |\
 672                          BRx_V)
 673
 674 #define CONFIG_SYS_OR9_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)     |\
 675                          ORxG_CSNT                        |\
 676                          ORxG_ACS_DIV1                    |\
 677                          ORxG_SCY_7_CLK                   |\
 678                          ORxG_SETA)
 679
 680 #endif  /* __CONFIG_H */