include/configs/CU824.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the CU824 board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_MPC824X          1
  45 #define CONFIG_MPC8240          1
  46 #define CONFIG_CU824            1
  47
  48 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  49
  50 #define CONFIG_CONS_INDEX       1
  51 #define CONFIG_BAUDRATE         9600
  52 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  53
  54 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  55
  56 #define CONFIG_BOOTCOMMAND      "bootm FE020000"        /* autoboot command     */
  57 #define CONFIG_BOOTDELAY        5
  58
  59 /*
  60  * BOOTP options
  61  */
  62 #define CONFIG_BOOTP_SUBNETMASK
  63 #define CONFIG_BOOTP_GATEWAY
  64 #define CONFIG_BOOTP_HOSTNAME
  65 #define CONFIG_BOOTP_BOOTPATH
  66 #define CONFIG_BOOTP_BOOTFILESIZE
  67
  68
  69 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  70
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #include <config_cmd_default.h>
  76
  77 #define CONFIG_CMD_BEDBUG
  78 #define CONFIG_CMD_DHCP
  79 #define CONFIG_CMD_PCI
  80 #define CONFIG_CMD_NFS
  81 #define CONFIG_CMD_SNTP
  82
  83
  84 /*
  85  * Miscellaneous configurable options
  86  */
  87 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  88 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  89 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  90
  91 #if 1
  92 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
  93 #endif
  94 #ifdef  CONFIG_SYS_HUSH_PARSER
  95 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
  96 #endif
  97
  98 /* Print Buffer Size
  99  */
 100 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 101
 102 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 103 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 104 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
 105
 106 /*-----------------------------------------------------------------------
 107  * Start addresses for the final memory configuration
 108  * (Set up by the startup code)
 109  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 110  */
 111 #define CONFIG_SYS_SDRAM_BASE       0x00000000
 112 #define CONFIG_SYS_FLASH_BASE       0xFF000000
 113
 114 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 115
 116 #define CONFIG_SYS_EUMB_ADDR        0xFCE00000
 117
 118 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 119
 120 #define CONFIG_SYS_MONITOR_LEN      (256 << 10) /* Reserve 256 kB for Monitor   */
 121 #define CONFIG_SYS_MALLOC_LEN       (128 << 10) /* Reserve 128 kB for malloc()  */
 122
 123 #define CONFIG_SYS_MEMTEST_START   0x00004000   /* memtest works on             */
 124 #define CONFIG_SYS_MEMTEST_END      0x02000000  /* 0 ... 32 MB in DRAM          */
 125
 126         /* Maximum amount of RAM.
 127          */
 128 #define CONFIG_SYS_MAX_RAM_SIZE    0x10000000
 129
 130
 131 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 132 #undef CONFIG_SYS_RAMBOOT
 133 #else
 134 #define CONFIG_SYS_RAMBOOT
 135 #endif
 136
 137
 138 /*-----------------------------------------------------------------------
 139  * Definitions for initial stack pointer and data area
 140  */
 141
 142         /* Size in bytes reserved for initial data
 143          */
 144 #define CONFIG_SYS_GBL_DATA_SIZE    128
 145
 146 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 147 #define CONFIG_SYS_INIT_RAM_END      0x1000
 148 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 149
 150 /*
 151  * NS16550 Configuration
 152  */
 153 #define CONFIG_SYS_NS16550
 154 #define CONFIG_SYS_NS16550_SERIAL
 155
 156 #define CONFIG_SYS_NS16550_REG_SIZE     4
 157
 158 #define CONFIG_SYS_NS16550_CLK          (14745600 / 2)
 159
 160 #define CONFIG_SYS_NS16550_COM1 0xFE800080
 161 #define CONFIG_SYS_NS16550_COM2 0xFE8000C0
 162
 163 /*
 164  * Low Level Configuration Settings
 165  * (address mappings, register initial values, etc.)
 166  * You should know what you are doing if you make changes here.
 167  * For the detail description refer to the MPC8240 user's manual.
 168  */
 169
 170 #define CONFIG_SYS_CLK_FREQ  33000000
 171 #define CONFIG_SYS_HZ                1000
 172
 173         /* Bit-field values for MCCR1.
 174          */
 175 #define CONFIG_SYS_ROMNAL           0
 176 #define CONFIG_SYS_ROMFAL           7
 177
 178         /* Bit-field values for MCCR2.
 179          */
 180 #define CONFIG_SYS_REFINT           430     /* Refresh interval                 */
 181
 182         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 183          */
 184 #define CONFIG_SYS_BSTOPRE          192
 185
 186         /* Bit-field values for MCCR3.
 187          */
 188 #define CONFIG_SYS_REFREC           2       /* Refresh to activate interval     */
 189 #define CONFIG_SYS_RDLAT            3       /* Data latancy from read command   */
 190
 191         /* Bit-field values for MCCR4.
 192          */
 193 #define CONFIG_SYS_PRETOACT         2       /* Precharge to activate interval   */
 194 #define CONFIG_SYS_ACTTOPRE         5       /* Activate to Precharge interval   */
 195 #define CONFIG_SYS_SDMODE_CAS_LAT  2        /* SDMODE CAS latancy               */
 196 #define CONFIG_SYS_SDMODE_WRAP      0       /* SDMODE wrap type                 */
 197 #define CONFIG_SYS_SDMODE_BURSTLEN 2        /* SDMODE Burst length              */
 198 #define CONFIG_SYS_ACTORW           2
 199 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 200
 201 /* Memory bank settings.
 202  * Only bits 20-29 are actually used from these vales to set the
 203  * start/end addresses. The upper two bits will always be 0, and the lower
 204  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 205  * address. Refer to the MPC8240 book.
 206  */
 207
 208 #define CONFIG_SYS_BANK0_START      0x00000000
 209 #define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 210 #define CONFIG_SYS_BANK0_ENABLE    1
 211 #define CONFIG_SYS_BANK1_START      0x3ff00000
 212 #define CONFIG_SYS_BANK1_END        0x3fffffff
 213 #define CONFIG_SYS_BANK1_ENABLE    0
 214 #define CONFIG_SYS_BANK2_START      0x3ff00000
 215 #define CONFIG_SYS_BANK2_END        0x3fffffff
 216 #define CONFIG_SYS_BANK2_ENABLE    0
 217 #define CONFIG_SYS_BANK3_START      0x3ff00000
 218 #define CONFIG_SYS_BANK3_END        0x3fffffff
 219 #define CONFIG_SYS_BANK3_ENABLE    0
 220 #define CONFIG_SYS_BANK4_START      0x3ff00000
 221 #define CONFIG_SYS_BANK4_END        0x3fffffff
 222 #define CONFIG_SYS_BANK4_ENABLE    0
 223 #define CONFIG_SYS_BANK5_START      0x3ff00000
 224 #define CONFIG_SYS_BANK5_END        0x3fffffff
 225 #define CONFIG_SYS_BANK5_ENABLE    0
 226 #define CONFIG_SYS_BANK6_START      0x3ff00000
 227 #define CONFIG_SYS_BANK6_END        0x3fffffff
 228 #define CONFIG_SYS_BANK6_ENABLE    0
 229 #define CONFIG_SYS_BANK7_START      0x3ff00000
 230 #define CONFIG_SYS_BANK7_END        0x3fffffff
 231 #define CONFIG_SYS_BANK7_ENABLE    0
 232
 233 #define CONFIG_SYS_ODCR     0xff
 234
 235 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 236 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 237
 238 #define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 239 #define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 240
 241 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 242 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 243
 244 #define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 245 #define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
 246
 247 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 248 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 249 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 250 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 251 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 252 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 253 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 254 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 255
 256 /*
 257  * For booting Linux, the board info and command line data
 258  * have to be in the first 8 MB of memory, since this is
 259  * the maximum mapped by the Linux kernel during initialization.
 260  */
 261 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 262
 263 /*-----------------------------------------------------------------------
 264  * FLASH organization
 265  */
 266 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* Max number of flash banks            */
 267 #define CONFIG_SYS_MAX_FLASH_SECT       39      /* Max number of sectors in one bank    */
 268
 269 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 270 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 271
 272         /* Warining: environment is not EMBEDDED in the U-Boot code.
 273          * It's stored in flash separately.
 274          */
 275 #define CONFIG_ENV_IS_IN_FLASH      1
 276 #if 0
 277 #define CONFIG_ENV_ADDR         0xFF008000
 278 #define CONFIG_ENV_SIZE         0x8000  /* Size of the Environment Sector       */
 279 #else
 280 #define CONFIG_ENV_ADDR         0xFFFC0000
 281 #define CONFIG_ENV_SIZE         0x4000  /* Size of the Environment              */
 282 #define CONFIG_ENV_OFFSET               0       /* starting right at the beginning      */
 283 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Size of the Environment Sector       */
 284 #endif
 285
 286 /*-----------------------------------------------------------------------
 287  * Cache Configuration
 288  */
 289 #define CONFIG_SYS_CACHELINE_SIZE       32
 290 #if defined(CONFIG_CMD_KGDB)
 291 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 292 #endif
 293
 294 /*-----------------------------------------------------------------------
 295  * PCI stuff
 296  *-----------------------------------------------------------------------
 297  */
 298 #define CONFIG_PCI                      /* include pci support                  */
 299 #undef CONFIG_PCI_PNP
 300
 301 #define CONFIG_NET_MULTI                /* Multi ethernet cards support         */
 302
 303 #define CONFIG_TULIP
 304 #define CONFIG_TULIP_USE_IO
 305
 306 #define CONFIG_SYS_ETH_DEV_FN        0x7800
 307 #define CONFIG_SYS_ETH_IOBASE        0x00104000
 308
 309 #define CONFIG_EEPRO100
 310 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 311 #define PCI_ENET0_IOADDR        0x00104000
 312 #define PCI_ENET0_MEMADDR       0x80000000
 313 #endif  /* __CONFIG_H */