include/configs/DK1S10.h

   1 /*
   2  * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
   3  * Stephan Linz <linz@li-pro.net>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * NIOS CPU configuration.
  29  *
  30  * Here we must define CPU dependencies. Any unsupported option have to
  31  * be defined with zero, example CPU without data cache / OCI:
  32  *
  33  *      #define CFG_NIOS_CPU_ICACHE     4096
  34  *      #define CFG_NIOS_CPU_DCACHE     0
  35  *      #define CFG_NIOS_CPU_OCI_BASE   0
  36  *      #define CFG_NIOS_CPU_OCI_SIZE   0
  37  */
  38
  39 #if     defined(CONFIG_NIOS_SAFE_32)
  40
  41 /* TODO */
  42
  43 #elif   defined(CONFIG_NIOS_STANDARD_32)
  44
  45 /* CPU core */
  46 #define CFG_NIOS_CPU_CLK        50000000        /* NIOS CPU clock       */
  47 #define CFG_NIOS_CPU_ICACHE     (4 * 1024)      /* instruction cache    */
  48 #define CFG_NIOS_CPU_DCACHE     (4 * 1024)      /* data cache           */
  49 #define CFG_NIOS_CPU_REG_NUMS   256             /* number of register   */
  50 #define CFG_NIOS_CPU_MUL        0               /* 16x16 MUL:   no(0)   */
  51                                                 /*              yes(1)  */
  52 #define CFG_NIOS_CPU_MSTEP      1               /* 16x16 MSTEP: no(0)   */
  53                                                 /*              yes(1)  */
  54 #define CFG_NIOS_CPU_STACK      0x008fff00      /* stack top    addr    */
  55 #define CFG_NIOS_CPU_VEC_BASE   0x008fff00      /* IRQ vectors  addr    */
  56 #define CFG_NIOS_CPU_VEC_SIZE   256             /*              size    */
  57 #define CFG_NIOS_CPU_VEC_NUMS   64              /*              numbers */
  58 #define CFG_NIOS_CPU_RST_VECT   0x00920000      /* RESET vector addr    */
  59 #define CFG_NIOS_CPU_DBG_CORE   0               /* CPU debug:   no(0)   */
  60                                                 /*              yes(1)  */
  61
  62 /* on-chip extensions */
  63 #define CFG_NIOS_CPU_RAM_BASE   0x00900000      /* on chip RAM  addr    */
  64 #define CFG_NIOS_CPU_RAM_SIZE   (64 * 1024)     /* 64 KB        size    */
  65
  66 #define CFG_NIOS_CPU_ROM_BASE   0x00920000      /* on chip ROM  addr    */
  67 #define CFG_NIOS_CPU_ROM_SIZE   (2 * 1024)      /*  2 KB        size    */
  68
  69 #define CFG_NIOS_CPU_OCI_BASE   0x00920800      /* OCI core     addr    */
  70 #define CFG_NIOS_CPU_OCI_SIZE   256             /*              size    */
  71
  72 /* timer */
  73 #define CFG_NIOS_CPU_TIMER_NUMS 2               /* number of timer      */
  74
  75 #define CFG_NIOS_CPU_TIMER0     0x00920940      /* TIMER0       addr    */
  76 #define CFG_NIOS_CPU_TIMER0_IRQ 16              /*              IRQ     */
  77 #define CFG_NIOS_CPU_TIMER0_PER 1000            /*  periode     usec    */
  78 #define CFG_NIOS_CPU_TIMER0_AR  0               /*  always run: no(0)   */
  79                                                 /*              yes(1)  */
  80 #define CFG_NIOS_CPU_TIMER0_FP  0               /*  fixed per:  no(0)   */
  81                                                 /*              yes(1)  */
  82 #define CFG_NIOS_CPU_TIMER0_SS  1               /*  snaphot:    no(0)   */
  83                                                 /*              yes(1)  */
  84
  85 #define CFG_NIOS_CPU_TIMER1     0x009209e0      /* TIMER1       addr    */
  86 #define CFG_NIOS_CPU_TIMER1_IRQ 50              /*              IRQ     */
  87 #define CFG_NIOS_CPU_TIMER1_PER 10000           /*  periode     usec    */
  88 #define CFG_NIOS_CPU_TIMER1_AR  1               /*  always run: no(0)   */
  89                                                 /*              yes(1)  */
  90 #define CFG_NIOS_CPU_TIMER1_FP  1               /*  fixed per:  no(0)   */
  91                                                 /*              yes(1)  */
  92 #define CFG_NIOS_CPU_TIMER1_SS  0               /*  snaphot:    no(0)   */
  93                                                 /*              yes(1)  */
  94
  95 /* serial i/o */
  96 #define CFG_NIOS_CPU_UART_NUMS  1               /* number of uarts      */
  97
  98 #define CFG_NIOS_CPU_UART0      0x00920900      /* UART0        addr    */
  99 #define CFG_NIOS_CPU_UART0_IRQ  25              /*              IRQ     */
 100 #define CFG_NIOS_CPU_UART0_BR   115200          /*  baudrate    var(0)  */
 101 #define CFG_NIOS_CPU_UART0_DB   8               /*  data bit            */
 102 #define CFG_NIOS_CPU_UART0_SB   1               /*  stop bit            */
 103 #define CFG_NIOS_CPU_UART0_PA   0               /*  parity      none(0) */
 104                                                 /*              odd(1)  */
 105                                                 /*              even(2) */
 106 #define CFG_NIOS_CPU_UART0_HS   0               /*  handshake:  no(0)   */
 107                                                 /*              crts(1) */
 108 #define CFG_NIOS_CPU_UART0_EOP  0               /*  eop reg:    no(0)   */
 109                                                 /*              yes(1)  */
 110
 111 /* parallel i/o */
 112 #define CFG_NIOS_CPU_PIO_NUMS   8               /* number of parports   */
 113
 114 #define CFG_NIOS_CPU_PIO0       0x00920960      /* PIO0         addr    */
 115 #define CFG_NIOS_CPU_PIO0_IRQ   40              /*              IRQ     */
 116 #define CFG_NIOS_CPU_PIO0_BITS  4               /*  number  of  bits    */
 117 #define CFG_NIOS_CPU_PIO0_TYPE  2               /*  io type:    tris(0) */
 118                                                 /*              out(1)  */
 119                                                 /*              in(2)   */
 120 #define CFG_NIOS_CPU_PIO0_CAP   1               /*  capture:    no(0)   */
 121                                                 /*              yes(1)  */
 122 #define CFG_NIOS_CPU_PIO0_EDGE  3               /*  edge type:  none(0) */
 123                                                 /*              fall(1) */
 124                                                 /*              rise(2) */
 125                                                 /*              any(3)  */
 126 #define CFG_NIOS_CPU_PIO0_ITYPE 2               /*  IRQ type:   none(0) */
 127                                                 /*              level(1)*/
 128                                                 /*              edge(2) */
 129
 130 #define CFG_NIOS_CPU_PIO1       0x00920970      /* PIO1         addr    */
 131 #undef  CFG_NIOS_CPU_PIO1_IRQ                   /*              w/o IRQ */
 132 #define CFG_NIOS_CPU_PIO1_BITS  11              /*  number  of  bits    */
 133 #define CFG_NIOS_CPU_PIO1_TYPE  0               /*  io type:    tris(0) */
 134                                                 /*              out(1)  */
 135                                                 /*              in(2)   */
 136 #define CFG_NIOS_CPU_PIO1_CAP   0               /*  capture:    no(0)   */
 137                                                 /*              yes(1)  */
 138 #define CFG_NIOS_CPU_PIO1_EDGE  0               /*  edge type:  none(0) */
 139                                                 /*              fall(1) */
 140                                                 /*              rise(2) */
 141                                                 /*              any(3)  */
 142 #define CFG_NIOS_CPU_PIO1_ITYPE 0               /*  IRQ type:   none(0) */
 143                                                 /*              level(1)*/
 144                                                 /*              edge(2) */
 145
 146 #define CFG_NIOS_CPU_PIO2       0x00920980      /* PIO2         addr    */
 147 #undef  CFG_NIOS_CPU_PIO2_IRQ                   /*              w/o IRQ */
 148 #define CFG_NIOS_CPU_PIO2_BITS  8               /*  number  of  bits    */
 149 #define CFG_NIOS_CPU_PIO2_TYPE  1               /*  io type:    tris(0) */
 150                                                 /*              out(1)  */
 151                                                 /*              in(2)   */
 152 #define CFG_NIOS_CPU_PIO2_CAP   0               /*  capture:    no(0)   */
 153                                                 /*              yes(1)  */
 154 #define CFG_NIOS_CPU_PIO2_EDGE  0               /*  edge type:  none(0) */
 155                                                 /*              fall(1) */
 156                                                 /*              rise(2) */
 157                                                 /*              any(3)  */
 158 #define CFG_NIOS_CPU_PIO2_ITYPE 0               /*  IRQ type:   none(0) */
 159                                                 /*              level(1)*/
 160                                                 /*              edge(2) */
 161
 162 #define CFG_NIOS_CPU_PIO3       0x00920990      /* PIO3         addr    */
 163 #undef  CFG_NIOS_CPU_PIO3_IRQ                   /*              w/o IRQ */
 164 #define CFG_NIOS_CPU_PIO3_BITS  16              /*  number  of  bits    */
 165 #define CFG_NIOS_CPU_PIO3_TYPE  1               /*  io type:    tris(0) */
 166                                                 /*              out(1)  */
 167                                                 /*              in(2)   */
 168 #define CFG_NIOS_CPU_PIO3_CAP   0               /*  capture:    no(0)   */
 169                                                 /*              yes(1)  */
 170 #define CFG_NIOS_CPU_PIO3_EDGE  0               /*  edge type:  none(0) */
 171                                                 /*              fall(1) */
 172                                                 /*              rise(2) */
 173                                                 /*              any(3)  */
 174 #define CFG_NIOS_CPU_PIO3_ITYPE 0               /*  IRQ type:   none(0) */
 175                                                 /*              level(1)*/
 176                                                 /*              edge(2) */
 177
 178 #define CFG_NIOS_CPU_PIO4       0x009209a0      /* PIO4         addr    */
 179 #undef  CFG_NIOS_CPU_PIO4_IRQ                   /*              w/o IRQ */
 180 #define CFG_NIOS_CPU_PIO4_BITS  1               /*  number  of  bits    */
 181 #define CFG_NIOS_CPU_PIO4_TYPE  0               /*  io type:    tris(0) */
 182                                                 /*              out(1)  */
 183                                                 /*              in(2)   */
 184 #define CFG_NIOS_CPU_PIO4_CAP   0               /*  capture:    no(0)   */
 185                                                 /*              yes(1)  */
 186 #define CFG_NIOS_CPU_PIO4_EDGE  0               /*  edge type:  none(0) */
 187                                                 /*              fall(1) */
 188                                                 /*              rise(2) */
 189                                                 /*              any(3)  */
 190 #define CFG_NIOS_CPU_PIO4_ITYPE 0               /*  IRQ type:   none(0) */
 191                                                 /*              level(1)*/
 192                                                 /*              edge(2) */
 193
 194 #define CFG_NIOS_CPU_PIO5       0x009209b0      /* PIO5         addr    */
 195 #define CFG_NIOS_CPU_PIO5_IRQ   35              /*              IRQ     */
 196 #define CFG_NIOS_CPU_PIO5_BITS  1               /*  number  of  bits    */
 197 #define CFG_NIOS_CPU_PIO5_TYPE  2               /*  io type:    tris(0) */
 198                                                 /*              out(1)  */
 199                                                 /*              in(2)   */
 200 #define CFG_NIOS_CPU_PIO5_CAP   1               /*  capture:    no(0)   */
 201                                                 /*              yes(1)  */
 202 #define CFG_NIOS_CPU_PIO5_EDGE  3               /*  edge type:  none(0) */
 203                                                 /*              fall(1) */
 204                                                 /*              rise(2) */
 205                                                 /*              any(3)  */
 206 #define CFG_NIOS_CPU_PIO5_ITYPE 2               /*  IRQ type:   none(0) */
 207                                                 /*              level(1)*/
 208                                                 /*              edge(2) */
 209
 210 #define CFG_NIOS_CPU_PIO6       0x009209c0      /* PIO6         addr    */
 211 #undef  CFG_NIOS_CPU_PIO6_IRQ                   /*              w/o IRQ */
 212 #define CFG_NIOS_CPU_PIO6_BITS  1               /*  number  of  bits    */
 213 #define CFG_NIOS_CPU_PIO6_TYPE  1               /*  io type:    tris(0) */
 214                                                 /*              out(1)  */
 215                                                 /*              in(2)   */
 216 #define CFG_NIOS_CPU_PIO6_CAP   0               /*  capture:    no(0)   */
 217                                                 /*              yes(1)  */
 218 #define CFG_NIOS_CPU_PIO6_EDGE  0               /*  edge type:  none(0) */
 219                                                 /*              fall(1) */
 220                                                 /*              rise(2) */
 221                                                 /*              any(3)  */
 222 #define CFG_NIOS_CPU_PIO6_ITYPE 0               /*  IRQ type:   none(0) */
 223                                                 /*              level(1)*/
 224                                                 /*              edge(2) */
 225
 226 #define CFG_NIOS_CPU_PIO7       0x009209d0      /* PIO7         addr    */
 227 #undef  CFG_NIOS_CPU_PIO7_IRQ                   /*              w/o IRQ */
 228 #define CFG_NIOS_CPU_PIO7_BITS  1               /*  number  of  bits    */
 229 #define CFG_NIOS_CPU_PIO7_TYPE  1               /*  io type:    tris(0) */
 230                                                 /*              out(1)  */
 231                                                 /*              in(2)   */
 232 #define CFG_NIOS_CPU_PIO7_CAP   0               /*  capture:    no(0)   */
 233                                                 /*              yes(1)  */
 234 #define CFG_NIOS_CPU_PIO7_EDGE  0               /*  edge type:  none(0) */
 235                                                 /*              fall(1) */
 236                                                 /*              rise(2) */
 237                                                 /*              any(3)  */
 238 #define CFG_NIOS_CPU_PIO7_ITYPE 0               /*  IRQ type:   none(0) */
 239                                                 /*              level(1)*/
 240                                                 /*              edge(2) */
 241
 242 /* IDE i/f */
 243 #define CFG_NIOS_CPU_IDE_NUMS   1               /* number of IDE contr. */
 244 #define CFG_NIOS_CPU_IDE0       0x00920a00      /* IDE0         addr    */
 245
 246 /* active serial memory i/f */
 247 #define CFG_NIOS_CPU_ASMI_NUMS  1               /* number of ASMI       */
 248 #define CFG_NIOS_CPU_ASMI0      0x00920b00      /* ASMI0        addr    */
 249 #define CFG_NIOS_CPU_ASMI0_IRQ  45              /*              IRQ     */
 250
 251 /* memory accessibility */
 252 #define CFG_NIOS_CPU_SRAM_BASE  0x00800000      /* board SRAM   addr    */
 253 #define CFG_NIOS_CPU_SRAM_SIZE  (1024 * 1024)   /*  1 MB        size    */
 254
 255 #define CFG_NIOS_CPU_SDRAM_BASE 0x01000000      /* board SDRAM  addr    */
 256 #define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024)  /* 16 MB        size    */
 257
 258 #define CFG_NIOS_CPU_FLASH_BASE 0x00000000      /* board Flash  addr    */
 259 #define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024)   /*  8 MB        size    */
 260
 261 /* LAN */
 262 #define CFG_NIOS_CPU_LAN_NUMS   1               /* number of LAN i/f    */
 263
 264 #define CFG_NIOS_CPU_LAN0_BASE  0x00910000      /* LAN0         addr    */
 265 #define CFG_NIOS_CPU_LAN0_OFFS  0x0300          /*              offset  */
 266 #define CFG_NIOS_CPU_LAN0_IRQ   30              /*              IRQ     */
 267 #define CFG_NIOS_CPU_LAN0_BUSW  32              /*              buswidth*/
 268 #define CFG_NIOS_CPU_LAN0_TYPE  0               /*      smc91111(0)     */
 269                                                 /*      cs8900(1)       */
 270                                                 /* ex:  alteramac(2)    */
 271
 272 /* symbolic redefinition (undef, if not present) */
 273 #define CFG_NIOS_CPU_USER_TIMER         0       /* TIMER0: users choice */
 274 #define CFG_NIOS_CPU_TICK_TIMER         1       /* TIMER1: tick (needed)*/
 275
 276 #define CFG_NIOS_CPU_BUTTON_PIO         0       /* PIO0: buttons        */
 277 #define CFG_NIOS_CPU_LCD_PIO            1       /* PIO1: ASCII LCD      */
 278 #define CFG_NIOS_CPU_LED_PIO            2       /* PIO2: LED bar        */
 279 #define CFG_NIOS_CPU_SEVENSEG_PIO       3       /* PIO3: 7-seg. display */
 280 #define CFG_NIOS_CPU_RECONF_PIO         4       /* PIO4: reconf pin     */
 281 #define CFG_NIOS_CPU_CFPRESENT_PIO      5       /* PIO5: CF present IRQ */
 282 #define CFG_NIOS_CPU_CFPOWER_PIO        6       /* PIO6: CF power/sw.   */
 283 #define CFG_NIOS_CPU_CFATASEL_PIO       7       /* PIO7: CF ATA select  */
 284
 285 #else
 286 #error *** CFG_ERROR: you have to setup right NIOS CPU configuration
 287 #endif
 288
 289 /*------------------------------------------------------------------------
 290  * BOARD/CPU -- TOP-LEVEL
 291  *----------------------------------------------------------------------*/
 292 #define CONFIG_NIOS             1               /* NIOS-32 core         */
 293 #define CONFIG_DK1S10           1               /* Stratix DK-1S10 board*/
 294 #define CONFIG_SYS_CLK_FREQ     CFG_NIOS_CPU_CLK/* 50 MHz core clock    */
 295 #define CFG_HZ                  1000            /* 1 msec time tick     */
 296 #undef  CFG_CLKS_IN_HZ
 297 #define CONFIG_BOARD_EARLY_INIT_F 1     /* enable early board-spec. init*/
 298
 299 /*------------------------------------------------------------------------
 300  * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
 301  *----------------------------------------------------------------------*/
 302 #if     (CFG_NIOS_CPU_SDRAM_SIZE != 0)
 303
 304 #define CFG_SDRAM_BASE          CFG_NIOS_CPU_SDRAM_BASE
 305 #define CFG_SDRAM_SIZE          CFG_NIOS_CPU_SDRAM_SIZE
 306
 307 #else
 308 #error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
 309 #endif
 310
 311 #define CFG_SRAM_BASE           CFG_NIOS_CPU_SRAM_BASE
 312 #define CFG_SRAM_SIZE           CFG_NIOS_CPU_SRAM_SIZE
 313 #define CFG_VECT_BASE           CFG_NIOS_CPU_VEC_BASE
 314
 315 /*------------------------------------------------------------------------
 316  * MEMORY ORGANIZATION - For the most part, you can put things pretty
 317  * much anywhere. This is pretty flexible for Nios. So here we make some
 318  * arbitrary choices & assume that the monitor is placed at the end of
 319  * a memory resource (so you must make sure TEXT_BASE is chosen
 320  * appropriately).
 321  *
 322  *      -The heap is placed below the monitor.
 323  *      -Global data is placed below the heap.
 324  *      -The stack is placed below global data (&grows down).
 325  *----------------------------------------------------------------------*/
 326 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256k         */
 327 #define CFG_GBL_DATA_SIZE       128             /* Global data size rsvd*/
 328 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
 329
 330 #define CFG_MONITOR_BASE        TEXT_BASE
 331 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 332 #define CFG_GBL_DATA_OFFSET     (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
 333 #define CFG_INIT_SP             CFG_GBL_DATA_OFFSET
 334
 335 /*------------------------------------------------------------------------
 336  * FLASH (AM29LV065D)
 337  *----------------------------------------------------------------------*/
 338 #if     (CFG_NIOS_CPU_FLASH_SIZE != 0)
 339
 340 #define CFG_FLASH_BASE          CFG_NIOS_CPU_FLASH_BASE
 341 #define CFG_FLASH_SIZE          CFG_NIOS_CPU_FLASH_SIZE
 342 #define CFG_MAX_FLASH_SECT      128             /* Max # sects per bank */
 343 #define CFG_MAX_FLASH_BANKS     1               /* Max # of flash banks */
 344 #define CFG_FLASH_ERASE_TOUT    8000            /* Erase timeout (msec) */
 345 #define CFG_FLASH_WRITE_TOUT    100             /* Write timeout (msec) */
 346 #define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size      */
 347
 348 #else
 349 #error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
 350 #endif
 351
 352 /*------------------------------------------------------------------------
 353  * ENVIRONMENT
 354  *----------------------------------------------------------------------*/
 355 #if     (CFG_NIOS_CPU_FLASH_SIZE != 0)
 356
 357 #define CFG_ENV_IS_IN_FLASH     1               /* Environment in flash */
 358 #define CFG_ENV_ADDR            CFG_FLASH_BASE  /* Mem addr of env      */
 359 #define CFG_ENV_SIZE            (64 * 1024)     /* 64 KByte (1 sector)  */
 360 #define CONFIG_ENV_OVERWRITE                    /* Serial/eth change Ok */
 361
 362 #else
 363 #define CFG_ENV_IS_NOWHERE      1               /* NO Environment       */
 364 #endif
 365
 366 /*------------------------------------------------------------------------
 367  * CONSOLE
 368  *----------------------------------------------------------------------*/
 369 #if     (CFG_NIOS_CPU_UART_NUMS != 0)
 370
 371 #define CFG_NIOS_CONSOLE        CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
 372
 373 #if     (CFG_NIOS_CPU_UART0_BR != 0)
 374 #define CFG_NIOS_FIXEDBAUD      1                  /* Baudrate is fixed */
 375 #define CONFIG_BAUDRATE         CFG_NIOS_CPU_UART0_BR
 376 #else
 377 #undef  CFG_NIOS_FIXEDBAUD
 378 #define CONFIG_BAUDRATE         115200
 379 #endif
 380
 381 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 382
 383 #else
 384 #error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
 385 #endif
 386
 387 /*------------------------------------------------------------------------
 388  * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT,
 389  * so an avalon bus timer is required.
 390  *----------------------------------------------------------------------*/
 391 #if     (CFG_NIOS_CPU_TIMER_NUMS != 0)
 392
 393 #if     (CFG_NIOS_CPU_TICK_TIMER == 0)
 394
 395 #error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h
 396
 397 #elif   (CFG_NIOS_CPU_TICK_TIMER == 1)
 398
 399 #define CFG_NIOS_TMRBASE        CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick   */
 400 #define CFG_NIOS_TMRIRQ         CFG_NIOS_CPU_TIMER1_IRQ
 401
 402 #if     (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
 403 #define CFG_NIOS_TMRMS          (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
 404 #else
 405 #error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
 406 #endif
 407
 408 #endif  /* CFG_NIOS_CPU_TICK_TIMER */
 409
 410 #else
 411 #error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
 412 #endif
 413
 414 /*------------------------------------------------------------------------
 415  * Ethernet -- needs work!
 416  *----------------------------------------------------------------------*/
 417 #if     (CFG_NIOS_CPU_LAN_NUMS == 1)
 418
 419 #if     (CFG_NIOS_CPU_LAN0_TYPE == 0)           /* LAN91C111            */
 420
 421         /****************************************************/
 422         /* !!! LAN91C111 works for NIOS with patch only !!! */
 423         /****************************************************/
 424 #define CONFIG_DRIVER_SMC91111                  /* Using SMC91c111      */
 425 #undef  CONFIG_SMC91111_EXT_PHY                 /* Internal PHY         */
 426 #define CONFIG_SMC91111_BASE    (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
 427
 428 #if     (CFG_NIOS_CPU_LAN0_BUSW == 32)
 429 #define CONFIG_SMC_USE_32_BIT   1
 430 #else   /* no */
 431 #undef  CONFIG_SMC_USE_32_BIT
 432 #endif
 433
 434 #elif   (CFG_NIOS_CPU_LAN0_TYPE == 1)           /* CS8900A              */
 435
 436         /********************************************/
 437         /* !!! CS8900 is __not__ tested on NIOS !!! */
 438         /********************************************/
 439 #define CONFIG_DRIVER_CS8900                    /* Using CS8900         */
 440 #define CS8900_BASE             (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
 441
 442 #if     (CFG_NIOS_CPU_LAN0_BUSW == 32)
 443 #undef  CS8900_BUS16
 444 #define CS8900_BUS32            1
 445 #else   /* no */
 446 #define CS8900_BUS16            1
 447 #undef  CS8900_BUS32
 448 #endif
 449
 450 #else
 451 #error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
 452 #endif
 453
 454 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
 455 #define CONFIG_NETMASK          255.255.255.0
 456 #define CONFIG_IPADDR           192.168.2.21
 457 #define CONFIG_SERVERIP         192.168.2.16
 458
 459 #else
 460 #error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
 461 #endif
 462
 463 /*------------------------------------------------------------------------
 464  * STATUS LEDs
 465  *----------------------------------------------------------------------*/
 466 #if     (CFG_NIOS_CPU_PIO_NUMS != 0)
 467
 468 #if     (CFG_NIOS_CPU_LED_PIO == 0)
 469
 470 #error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
 471
 472 #elif   (CFG_NIOS_CPU_LED_PIO == 1)
 473
 474 #error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
 475
 476 #elif   (CFG_NIOS_CPU_LED_PIO == 2)
 477
 478 #define STATUS_LED_BASE                 CFG_NIOS_CPU_PIO2
 479 #define STATUS_LED_BITS                 CFG_NIOS_CPU_PIO2_BITS
 480 #define STATUS_LED_ACTIVE               1 /* LED on for bit == 1 */
 481
 482 #if     (CFG_NIOS_CPU_PIO2_TYPE == 1)
 483 #define STATUS_LED_WRONLY               1
 484 #else
 485 #undef  STATUS_LED_WRONLY
 486 #endif
 487
 488 #elif   (CFG_NIOS_CPU_LED_PIO == 3)
 489
 490 #error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
 491
 492 #elif   (CFG_NIOS_CPU_LED_PIO == 4)
 493
 494 #error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
 495
 496 #elif   (CFG_NIOS_CPU_LED_PIO == 5)
 497
 498 #error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
 499
 500 #elif   (CFG_NIOS_CPU_LED_PIO == 6)
 501
 502 #error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
 503
 504 #elif   (CFG_NIOS_CPU_LED_PIO == 7)
 505
 506 #error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
 507
 508 #elif   (CFG_NIOS_CPU_LED_PIO == 8)
 509
 510 #error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
 511
 512 #elif   (CFG_NIOS_CPU_LED_PIO == 9)
 513
 514 #error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
 515
 516 #else
 517 #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
 518 #endif
 519
 520 #define CONFIG_STATUS_LED               1 /* enable status led driver */
 521
 522 #define STATUS_LED_BIT                  (1 << 0)        /* LED[0] */
 523 #define STATUS_LED_STATE                STATUS_LED_BLINKING
 524 #define STATUS_LED_BOOT_STATE           STATUS_LED_OFF
 525 #define STATUS_LED_PERIOD               (CFG_HZ / 10)   /* ca. 1 Hz */
 526 #define STATUS_LED_BOOT                 0               /* boot LED */
 527
 528 #if     (STATUS_LED_BITS > 1)
 529 #define STATUS_LED_BIT1                 (1 << 1)        /* LED[1] */
 530 #define STATUS_LED_STATE1               STATUS_LED_OFF
 531 #define STATUS_LED_PERIOD1              (CFG_HZ / 50)   /* ca. 5 Hz */
 532 #define STATUS_LED_RED                  1               /* fail LED */
 533 #endif
 534
 535 #if     (STATUS_LED_BITS > 2)
 536 #define STATUS_LED_BIT2                 (1 << 2)        /* LED[2] */
 537 #define STATUS_LED_STATE2               STATUS_LED_OFF
 538 #define STATUS_LED_PERIOD2              (CFG_HZ / 10)   /* ca. 1 Hz */
 539 #define STATUS_LED_YELLOW               2               /* info LED */
 540 #endif
 541
 542 #if     (STATUS_LED_BITS > 3)
 543 #define STATUS_LED_BIT3                 (1 << 3)        /* LED[3] */
 544 #define STATUS_LED_STATE3               STATUS_LED_OFF
 545 #define STATUS_LED_PERIOD3              (CFG_HZ / 10)   /* ca. 1 Hz */
 546 #define STATUS_LED_GREEN                3               /* info LED */
 547 #endif
 548
 549 #define STATUS_LED_PAR                  1 /* makes status_led.h happy */
 550
 551 #endif  /* CFG_NIOS_CPU_PIO_NUMS */
 552
 553 /*------------------------------------------------------------------------
 554  * SEVEN SEGMENT LED DISPLAY
 555  *----------------------------------------------------------------------*/
 556 #if     (CFG_NIOS_CPU_PIO_NUMS != 0)
 557
 558 #if     (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
 559
 560 #error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
 561
 562 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
 563
 564 #error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
 565
 566 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
 567
 568 #error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h
 569
 570 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
 571
 572 #define SEVENSEG_BASE                   CFG_NIOS_CPU_PIO3
 573 #define SEVENSEG_BITS                   CFG_NIOS_CPU_PIO3_BITS
 574 #define SEVENSEG_ACTIVE                 0 /* LED on for bit == 1 */
 575
 576 #if     (CFG_NIOS_CPU_PIO3_TYPE == 1)
 577 #define SEVENSEG_WRONLY                 1
 578 #else
 579 #undef  SEVENSEG_WRONLY
 580 #endif
 581
 582 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
 583
 584 #error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
 585
 586 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
 587
 588 #error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
 589
 590 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
 591
 592 #error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
 593
 594 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
 595
 596 #error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
 597
 598 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
 599
 600 #error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
 601
 602 #elif   (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
 603
 604 #error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
 605
 606 #else
 607 #error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
 608 #endif
 609
 610 #define CONFIG_SEVENSEG                 1 /* enable seven segment led driver */
 611
 612 /*
 613  * Dual 7-Segment Display pin assignment -- read more in your
 614  * "Nios Development Board Reference Manual"
 615  *
 616  *
 617  *    (U8) HI:D[15..8]     (U9) LO:D[7..0]
 618  *         ______               ______
 619  *        |  D14 |             |  D6  |
 620  *        |      |             |      |
 621  *      D9|      |D13        D1|      |D5
 622  *        |______|             |______|                  ___
 623  *        |  D8  |             |  D0  |                 | A |
 624  *        |      |             |      |                F|___|B
 625  *     D10|      |D12        D2|      |D4               | G |
 626  *        |______|             |______|                E|___|C
 627  *           D11  *               D3   *                  D  *
 628  *                D15                  D7                    DP
 629  *
 630  */
 631 #define SEVENSEG_DIGIT_HI_LO_EQUAL      1       /* high nibble equal low nibble */
 632 #define SEVENSEG_DIGIT_A                (1 << 6) /* bit 6 is segment A */
 633 #define SEVENSEG_DIGIT_B                (1 << 5) /* bit 5 is segment B */
 634 #define SEVENSEG_DIGIT_C                (1 << 4) /* bit 4 is segment C */
 635 #define SEVENSEG_DIGIT_D                (1 << 3) /* bit 3 is segment D */
 636 #define SEVENSEG_DIGIT_E                (1 << 2) /* bit 2 is segment E */
 637 #define SEVENSEG_DIGIT_F                (1 << 1) /* bit 1 is segment F */
 638 #define SEVENSEG_DIGIT_G                (1 << 0) /* bit 0 is segment G */
 639 #define SEVENSEG_DIGIT_DP               (1 << 7) /* bit 7 is decimal point */
 640
 641 #endif  /* CFG_NIOS_CPU_PIO_NUMS */
 642
 643 /*------------------------------------------------------------------------
 644  * COMMANDS
 645  *----------------------------------------------------------------------*/
 646 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 647                                  CFG_CMD_ASKENV | \
 648                                  CFG_CMD_BEDBUG | \
 649                                  CFG_CMD_BMP    | \
 650                                  CFG_CMD_BSP    | \
 651                                  CFG_CMD_CACHE  | \
 652                                  CFG_CMD_DATE   | \
 653                                  CFG_CMD_DOC    | \
 654                                  CFG_CMD_DTT    | \
 655                                  CFG_CMD_EEPROM | \
 656                                  CFG_CMD_ELF    | \
 657                                  CFG_CMD_FAT    | \
 658                                  CFG_CMD_FDC    | \
 659                                  CFG_CMD_FDOS   | \
 660                                  CFG_CMD_HWFLOW | \
 661                                  CFG_CMD_IDE    | \
 662                                  CFG_CMD_I2C    | \
 663                                  CFG_CMD_JFFS2  | \
 664                                  CFG_CMD_KGDB   | \
 665                                  CFG_CMD_NAND   | \
 666                                  CFG_CMD_MMC    | \
 667                                  CFG_CMD_MII    | \
 668                                  CFG_CMD_PCI    | \
 669                                  CFG_CMD_PCMCIA | \
 670                                  CFG_CMD_SCSI   | \
 671                                  CFG_CMD_SPI    | \
 672                                  CFG_CMD_VFD    | \
 673                                  CFG_CMD_USB    ) )
 674
 675
 676 #include <cmd_confdefs.h>
 677
 678 /*------------------------------------------------------------------------
 679  * KGDB
 680  *----------------------------------------------------------------------*/
 681 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 682 #define CONFIG_KGDB_BAUDRATE    9600
 683 #endif
 684
 685 /*------------------------------------------------------------------------
 686  * MISC
 687  *----------------------------------------------------------------------*/
 688 #define CFG_LONGHELP                        /* undef to save memory     */
 689 #define CFG_PROMPT              "DK1S10 > " /* Monitor Command Prompt   */
 690 #define CFG_CBSIZE              256         /* Console I/O Buffer Size  */
 691 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 692 #define CFG_MAXARGS             16          /* max number of command args*/
 693 #define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size */
 694
 695 #if     (CFG_SRAM_SIZE != 0)
 696 #define CFG_LOAD_ADDR           CFG_SRAM_BASE   /* Default load address */
 697 #else
 698 #undef  CFG_LOAD_ADDR
 699 #endif
 700
 701 #if     (CFG_SDRAM_SIZE != 0)
 702 #define CFG_MEMTEST_START       CFG_SDRAM_BASE  /* SDRAM til stack area */
 703 #define CFG_MEMTEST_END         (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
 704 #else
 705 #undef  CFG_MEMTEST_START
 706 #undef  CFG_MEMTEST_END
 707 #endif
 708
 709
 710 #endif  /* __CONFIG_H */