include/configs/DP405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_DP405            1       /* ...on a DP405 board          */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFFD0000
  24
  25 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  26 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  27
  28 #define CONFIG_SYS_CLK_FREQ     33333300 /* external frequency to pll   */
  29
  30 #define CONFIG_BAUDRATE         9600
  31 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  32
  33 #undef  CONFIG_BOOTARGS
  34 #undef  CONFIG_BOOTCOMMAND
  35
  36 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  37
  38 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  39
  40 /*
  41  * Command line configuration.
  42  */
  43 #include <config_cmd_default.h>
  44
  45 #define CONFIG_CMD_BSP
  46 #define CONFIG_CMD_ELF
  47 #define CONFIG_CMD_I2C
  48 #define CONFIG_CMD_EEPROM
  49
  50 #undef CONFIG_CMD_NET
  51 #undef CONFIG_CMD_NFS
  52
  53 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  54
  55 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  56
  57 #define CONFIG_PRAM             2       /* reserve 2 kB "protected RAM" */
  58
  59 /*
  60  * Miscellaneous configurable options
  61  */
  62 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  63
  64 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  65
  66 #if defined(CONFIG_CMD_KGDB)
  67 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  68 #else
  69 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  70 #endif
  71 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  72 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  73 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  74
  75 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  76
  77 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  78
  79 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  80 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  81
  82 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  83 #define CONFIG_SYS_NS16550
  84 #define CONFIG_SYS_NS16550_SERIAL
  85 #define CONFIG_SYS_NS16550_REG_SIZE     1
  86 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  87
  88 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
  89 #define CONFIG_SYS_BASE_BAUD        691200
  90
  91 /* The following table includes the supported baudrates */
  92 #define CONFIG_SYS_BAUDRATE_TABLE       \
  93         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
  94          57600, 115200, 230400, 460800, 921600 }
  95
  96 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
  97 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
  98
  99 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 100
 101 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 102
 103 /*
 104  * For booting Linux, the board info and command line data
 105  * have to be in the first 8 MB of memory, since this is
 106  * the maximum mapped by the Linux kernel during initialization.
 107  */
 108 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 109 /*-----------------------------------------------------------------------
 110  * FLASH organization
 111  */
 112 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 113
 114 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 115 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 116
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 119
 120 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 121 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 122 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 123 /*
 124  * The following defines are added for buggy IOP480 byte interface.
 125  * All other boards should use the standard values (CPCI405 etc.)
 126  */
 127 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 128 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 129 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 130
 131 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 132
 133 /*-----------------------------------------------------------------------
 134  * Start addresses for the final memory configuration
 135  * (Set up by the startup code)
 136  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 137  */
 138 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 139 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 140 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 141 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 142 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 143
 144 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 145 # define CONFIG_SYS_RAMBOOT             1
 146 #else
 147 # undef CONFIG_SYS_RAMBOOT
 148 #endif
 149
 150 /*-----------------------------------------------------------------------
 151  * Environment Variable setup
 152  */
 153 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 154 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 155 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 156                                    /* total size of a CAT24WC16 is 2048 bytes */
 157
 158 /*-----------------------------------------------------------------------
 159  * I2C EEPROM (CAT24WC16) for environment
 160  */
 161 #define CONFIG_SYS_I2C
 162 #define CONFIG_SYS_I2C_PPC4XX
 163 #define CONFIG_SYS_I2C_PPC4XX_CH0
 164 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 165 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 166
 167 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 168 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 169 /* mask of address bits that overflow into the "EEPROM chip address"    */
 170 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 171 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 172                                         /* 16 byte page write mode using*/
 173                                         /* last 4 bits of the address   */
 174 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 175
 176 /*-----------------------------------------------------------------------
 177  * External Bus Controller (EBC) Setup
 178  */
 179
 180 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 181
 182 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 183 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 184 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 185
 186 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 187 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 188 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 189
 190 /*-----------------------------------------------------------------------
 191  * FPGA stuff
 192  */
 193 /* FPGA program pin configuration */
 194 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 195 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 196 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 197 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 198 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 199
 200 /*-----------------------------------------------------------------------
 201  * Definitions for initial stack pointer and data area (in data cache)
 202  */
 203 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 204 #define CONFIG_SYS_TEMP_STACK_OCM         1
 205
 206 /* On Chip Memory location */
 207 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 208 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 209 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 210 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 211
 212 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 213 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 214
 215 /*-----------------------------------------------------------------------
 216  * Definitions for GPIO setup (PPC405EP specific)
 217  *
 218  * GPIO0[0]     - External Bus Controller BLAST output
 219  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 220  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 221  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 222  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 223  * GPIO0[24-27] - UART0 control signal inputs/outputs
 224  * GPIO0[28-29] - UART1 data signal input/output
 225  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 226  */
 227 /* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 228 /* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 229 /* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 230 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 231 #define CONFIG_SYS_GPIO0_OSRL           0x40000540  /*  0 ... 15 */
 232 #define CONFIG_SYS_GPIO0_OSRH           0x00000110  /* 16 ... 31 */
 233 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000  /*  0 ... 15 */
 234 #define CONFIG_SYS_GPIO0_ISR1H          0x14000045  /* 16 ... 31 */
 235 #define CONFIG_SYS_GPIO0_TSRL           0x00000000  /*  0 ... 15 */
 236 #define CONFIG_SYS_GPIO0_TSRH           0x00000000  /* 16 ... 31 */
 237 #define CONFIG_SYS_GPIO0_TCR            0xB7FE0014  /*  0 ... 31 */
 238
 239 /*
 240  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 241  * This value will be set if iic boot eprom is disabled.
 242  */
 243 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 244 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 245
 246 #endif  /* __CONFIG_H */