include/configs/DP405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_DP405            1       /* ...on a DP405 board          */
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xFFFD0000
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333300 /* external frequency to pll   */
  46
  47 #define CONFIG_BAUDRATE         9600
  48 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  49
  50 #undef  CONFIG_BOOTARGS
  51 #undef  CONFIG_BOOTCOMMAND
  52
  53 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  54
  55 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  56
  57 /*
  58  * Command line configuration.
  59  */
  60 #include <config_cmd_default.h>
  61
  62 #define CONFIG_CMD_BSP
  63 #define CONFIG_CMD_ELF
  64 #define CONFIG_CMD_I2C
  65 #define CONFIG_CMD_EEPROM
  66
  67 #undef CONFIG_CMD_NET
  68 #undef CONFIG_CMD_NFS
  69
  70 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  71
  72 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  73
  74 #define CONFIG_PRAM             2       /* reserve 2 kB "protected RAM" */
  75
  76 /*
  77  * Miscellaneous configurable options
  78  */
  79 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  80 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  81
  82 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  83
  84 #if defined(CONFIG_CMD_KGDB)
  85 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  86 #else
  87 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  88 #endif
  89 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  90 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  91 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  92
  93 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  94
  95 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  96
  97 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  98 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  99
 100 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 101 #define CONFIG_SYS_NS16550
 102 #define CONFIG_SYS_NS16550_SERIAL
 103 #define CONFIG_SYS_NS16550_REG_SIZE     1
 104 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 105
 106 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 107 #define CONFIG_SYS_BASE_BAUD        691200
 108
 109 /* The following table includes the supported baudrates */
 110 #define CONFIG_SYS_BAUDRATE_TABLE       \
 111         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 112          57600, 115200, 230400, 460800, 921600 }
 113
 114 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 115 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 116
 117 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 118
 119 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 120
 121 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 122
 123 /*
 124  * For booting Linux, the board info and command line data
 125  * have to be in the first 8 MB of memory, since this is
 126  * the maximum mapped by the Linux kernel during initialization.
 127  */
 128 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 129 /*-----------------------------------------------------------------------
 130  * FLASH organization
 131  */
 132 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 133
 134 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 135 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 136
 137 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 138 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 139
 140 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 141 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 142 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 143 /*
 144  * The following defines are added for buggy IOP480 byte interface.
 145  * All other boards should use the standard values (CPCI405 etc.)
 146  */
 147 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 148 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 149 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 150
 151 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 152
 153 /*-----------------------------------------------------------------------
 154  * Start addresses for the final memory configuration
 155  * (Set up by the startup code)
 156  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 157  */
 158 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 159 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_MONITOR_BASE
 160 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 161 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 162 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
 163
 164 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 165 # define CONFIG_SYS_RAMBOOT             1
 166 #else
 167 # undef CONFIG_SYS_RAMBOOT
 168 #endif
 169
 170 /*-----------------------------------------------------------------------
 171  * Environment Variable setup
 172  */
 173 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 174 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 175 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 176                                    /* total size of a CAT24WC16 is 2048 bytes */
 177
 178 /*-----------------------------------------------------------------------
 179  * I2C EEPROM (CAT24WC16) for environment
 180  */
 181 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 182 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 183 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 184 #define CONFIG_SYS_I2C_SLAVE            0x7F
 185
 186 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 187 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 188 /* mask of address bits that overflow into the "EEPROM chip address"    */
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 191                                         /* 16 byte page write mode using*/
 192                                         /* last 4 bits of the address   */
 193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 194
 195 /*-----------------------------------------------------------------------
 196  * External Bus Controller (EBC) Setup
 197  */
 198
 199 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 200
 201 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 202 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 203 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 204
 205 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 206 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 207 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 208
 209 /*-----------------------------------------------------------------------
 210  * FPGA stuff
 211  */
 212 /* FPGA program pin configuration */
 213 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* JTAG TMS pin (ppc output)     */
 214 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* JTAG TCK pin (ppc output)     */
 215 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 216 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* unused (ppc input)            */
 217 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 218
 219 /*-----------------------------------------------------------------------
 220  * Definitions for initial stack pointer and data area (in data cache)
 221  */
 222 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 223 #define CONFIG_SYS_TEMP_STACK_OCM         1
 224
 225 /* On Chip Memory location */
 226 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 227 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 228 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 229 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 230
 231 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 232 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 233
 234 /*-----------------------------------------------------------------------
 235  * Definitions for GPIO setup (PPC405EP specific)
 236  *
 237  * GPIO0[0]     - External Bus Controller BLAST output
 238  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 239  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 240  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 241  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 242  * GPIO0[24-27] - UART0 control signal inputs/outputs
 243  * GPIO0[28-29] - UART1 data signal input/output
 244  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 245  */
 246 /* GPIO Input:          OSR=00, ISR=00, TSR=00, TCR=0 */
 247 /* GPIO Output:         OSR=00, ISR=00, TSR=00, TCR=1 */
 248 /* Alt. Funtion Input:  OSR=00, ISR=01, TSR=00, TCR=0 */
 249 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
 250 #define CONFIG_SYS_GPIO0_OSRL           0x40000540  /*  0 ... 15 */
 251 #define CONFIG_SYS_GPIO0_OSRH           0x00000110  /* 16 ... 31 */
 252 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000  /*  0 ... 15 */
 253 #define CONFIG_SYS_GPIO0_ISR1H          0x14000045  /* 16 ... 31 */
 254 #define CONFIG_SYS_GPIO0_TSRL           0x00000000  /*  0 ... 15 */
 255 #define CONFIG_SYS_GPIO0_TSRH           0x00000000  /* 16 ... 31 */
 256 #define CONFIG_SYS_GPIO0_TCR            0xB7FE0014  /*  0 ... 31 */
 257
 258 /*
 259  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 260  * This value will be set if iic boot eprom is disabled.
 261  */
 262 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 263 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 264
 265 #endif  /* __CONFIG_H */