include/configs/DU440.h

   1 /*
   2  * (C) Copyright 2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * based on the Sequoia board configuration by
   6  * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  **********************************************************************
  26  * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
  27  **********************************************************************
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_DU440            1               /* Board is esd DU440   */
  36 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  37 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  38 #define CONFIG_SYS_CLK_FREQ     33333400        /* external freq to pll */
  39
  40 #ifndef CONFIG_SYS_TEXT_BASE
  41 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  42 #endif
  43
  44 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  45 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  46 #define CONFIG_LAST_STAGE_INIT  1               /* last_stage_init      */
  47
  48 /*
  49  * Base addresses -- Note these are effective addresses where the
  50  * actual resources get mapped (not physical addresses)
  51  */
  52 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384 kB for Monitor */
  53 #define CONFIG_SYS_MALLOC_LEN           (8 << 20)       /* Reserve 8 MB for malloc()  */
  54
  55 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  56 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  57 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  58 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  59 #define CONFIG_SYS_NAND0_ADDR           0xd0000000      /* NAND Flash           */
  60 #define CONFIG_SYS_NAND1_ADDR           0xd0100000      /* NAND Flash           */
  61 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  62 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  63 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  64 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  65 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  66 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  67 #define CONFIG_SYS_PCI_IOBASE           0xe8000000
  68 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  PCI_VENDOR_ID_ESDGMBH
  69 #define CONFIG_SYS_PCI_SUBSYS_ID        0x0444          /* device ID for DU440 */
  70
  71 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  72 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  73 #define CONFIG_SYS_USB_HOST             0xe0000400
  74
  75 /*
  76  * Initial RAM & stack pointer
  77  */
  78 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  79 #define CONFIG_SYS_INIT_RAM_OCM 1               /* OCM as init ram      */
  80 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  81
  82 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  83 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  84 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  85
  86 /*
  87  * Serial Port
  88  */
  89 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  90 #define CONFIG_SYS_NS16550
  91 #define CONFIG_SYS_NS16550_SERIAL
  92 #define CONFIG_SYS_NS16550_REG_SIZE     1
  93 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  94 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  95 #define CONFIG_BAUDRATE         115200
  96
  97 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
  98         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  99
 100 /*
 101  * Video Port
 102  */
 103 #define CONFIG_VIDEO
 104 #define CONFIG_VIDEO_SMI_LYNXEM
 105 #define CONFIG_CFB_CONSOLE
 106 #define CONFIG_VIDEO_LOGO
 107 #define CONFIG_VGA_AS_SINGLE_DEVICE
 108 #define CONFIG_SPLASH_SCREEN
 109 #define CONFIG_SPLASH_SCREEN_ALIGN
 110 #define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
 111 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
 112 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
 113 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 114 #define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
 115
 116 /*
 117  * Environment
 118  */
 119 #define CONFIG_ENV_IS_IN_EEPROM    1    /* use FLASH for environment vars */
 120
 121 /*
 122  * FLASH related
 123  */
 124 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible */
 125 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver       */
 126
 127 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 128
 129 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 130 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 131
 132 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 133 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 134
 135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 136 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
 137 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 138
 139 #define CONFIG_SYS_FLASH_EMPTY_INFO
 140 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 141
 142 #ifdef CONFIG_ENV_IS_IN_FLASH
 143 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 144 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 145 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 146
 147 /* Address and size of Redundant Environment Sector     */
 148 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 149 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 150 #endif
 151
 152 #ifdef CONFIG_ENV_IS_IN_EEPROM
 153 #define CONFIG_ENV_OFFSET               0       /* environment starts at */
 154                                         /* the beginning of the EEPROM */
 155 #define CONFIG_ENV_SIZE         0x1000 /* 4096 bytes may be used for env vars */
 156 #endif
 157
 158 /*
 159  * DDR SDRAM
 160  */
 161 #define CONFIG_SYS_MBYTES_SDRAM        (1024)   /* 512 MiB      TODO: remove    */
 162 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 163 #define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
 164                                         /* 440EPx errata CHIP 11        */
 165 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 166 #define CONFIG_DDR_ECC                  /* Use ECC when available       */
 167 #define SPD_EEPROM_ADDRESS      {0x50}
 168 #define CONFIG_PROG_SDRAM_TLB
 169
 170 /*
 171  * I2C
 172  */
 173 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 174 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 175 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 176 #define CONFIG_SYS_I2C_SLAVE            0x7F
 177 #define CONFIG_I2C_MULTI_BUS    1
 178
 179 #define CONFIG_SYS_SPD_BUS_NUM         0
 180 #define IIC1_MCP3021_ADDR       0x4d
 181 #define IIC1_USB2507_ADDR       0x2c
 182 #ifdef CONFIG_I2C_MULTI_BUS
 183 #define CONFIG_SYS_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
 184 #endif
 185 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 186 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54
 187 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 188 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
 189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 190 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
 191
 192 #define CONFIG_SYS_EEPROM_WREN         1
 193 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 194
 195 /*
 196  * standard dtt sensor configuration - bottom bit will determine local or
 197  * remote sensor of the TMP401
 198  */
 199 #define CONFIG_DTT_SENSORS              { 0, 1 }
 200
 201 /*
 202  * The PMC440 uses a TI TMP401 temperature sensor. This part
 203  * is basically compatible to the ADM1021 that is supported
 204  * by U-Boot.
 205  *
 206  * - i2c addr 0x4c
 207  * - conversion rate 0x02 = 0.25 conversions/second
 208  * - ALERT ouput disabled
 209  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 210  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 211  */
 212 #define CONFIG_DTT_ADM1021
 213 #define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 214
 215 /*
 216  * RTC stuff
 217  */
 218 #define CONFIG_RTC_DS1338
 219 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 220
 221 #undef  CONFIG_BOOTARGS
 222
 223 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 224         "netdev=eth0\0"                                                 \
 225         "ethrotate=no\0"                                                \
 226         "hostname=du440\0"                                              \
 227         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 228                 "nfsroot=${serverip}:${rootpath}\0"                     \
 229         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 230         "addip=setenv bootargs ${bootargs} "                            \
 231                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 232                 ":${hostname}:${netdev}:off panic=1\0"                  \
 233         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 234         "flash_self=run ramargs addip addtty optargs;"                  \
 235                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 236         "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;"  \
 237                 "bootm\0"                                               \
 238         "rootpath=/tftpboot/du440/target_root_du440\0"                  \
 239         "img=/tftpboot/du440/uImage\0"                                  \
 240         "kernel_addr=FFC00000\0"                                        \
 241         "ramdisk_addr=FFE00000\0"                                       \
 242         "initrd_high=30000000\0"                                        \
 243         "load=tftp 100000 /tftpboot/du440/u-boot.bin\0"                 \
 244         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 245                 "cp.b 100000 FFFA0000 60000\0"                          \
 246         ""
 247
 248 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 249
 250 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds     */
 251
 252 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 253 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 254
 255 #ifndef __ASSEMBLY__
 256 int du440_phy_addr(int devnum);
 257 #endif
 258
 259 #define CONFIG_PPC4xx_EMAC
 260 #define CONFIG_IBM_EMAC4_V4     1
 261 #define CONFIG_MII              1       /* MII PHY management           */
 262 #define CONFIG_PHY_ADDR         du440_phy_addr(0) /* PHY address        */
 263
 264 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 265 #undef CONFIG_PHY_GIGE                  /* no GbE detection             */
 266
 267 #define CONFIG_HAS_ETH0
 268 #define CONFIG_SYS_RX_ETH_BUFFER        128
 269
 270 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 271 #define CONFIG_PHY1_ADDR        du440_phy_addr(1)
 272
 273 /*
 274  * USB
 275  */
 276 #define CONFIG_USB_OHCI_NEW
 277 #define CONFIG_USB_STORAGE
 278 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 279
 280 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 281 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 282 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "du440"
 283 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 284
 285 /* Comment this out to enable USB 1.1 device */
 286 #define USB_2_0_DEVICE
 287
 288 /* Partitions */
 289 #define CONFIG_MAC_PARTITION
 290 #define CONFIG_DOS_PARTITION
 291 #define CONFIG_ISO_PARTITION
 292
 293 #include <config_cmd_default.h>
 294
 295 #define CONFIG_CMD_ASKENV
 296 #define CONFIG_CMD_BMP
 297 #define CONFIG_CMD_BSP
 298 #define CONFIG_CMD_DATE
 299 #define CONFIG_CMD_DHCP
 300 #define CONFIG_CMD_DIAG
 301 #define CONFIG_CMD_DTT
 302 #define CONFIG_CMD_EEPROM
 303 #define CONFIG_CMD_ELF
 304 #define CONFIG_CMD_FAT
 305 #define CONFIG_CMD_I2C
 306 #define CONFIG_CMD_IRQ
 307 #define CONFIG_CMD_MII
 308 #define CONFIG_CMD_NAND
 309 #define CONFIG_CMD_NET
 310 #define CONFIG_CMD_NFS
 311 #define CONFIG_CMD_PCI
 312 #define CONFIG_CMD_PING
 313 #define CONFIG_CMD_REGINFO
 314 #define CONFIG_CMD_SDRAM
 315 #define CONFIG_CMD_SOURCE
 316 #define CONFIG_CMD_USB
 317
 318 #define CONFIG_SUPPORT_VFAT
 319
 320 /*
 321  * Miscellaneous configurable options
 322  */
 323 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 324 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 325 #if defined(CONFIG_CMD_KGDB)
 326 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 327 #else
 328 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 329 #endif
 330 /* Print Buffer Size */
 331 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 332 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 333 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 334
 335 #define CONFIG_SYS_MEMTEST_START        0x00400000 /* memtest works on          */
 336 #define CONFIG_SYS_MEMTEST_END          0x3f000000 /* 4 ... < 1GB DRAM  */
 337
 338 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 339 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 340
 341 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 342
 343 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 344 #define CONFIG_LOOPW            1       /* enable loopw command         */
 345 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 346 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 347 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 348
 349 #define CONFIG_AUTOBOOT_KEYED   1
 350 #define CONFIG_AUTOBOOT_PROMPT  \
 351         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 352 #define CONFIG_AUTOBOOT_DELAY_STR "d"
 353 #define CONFIG_AUTOBOOT_STOP_STR " "
 354
 355 /*
 356  * PCI stuff
 357  */
 358 #define CONFIG_PCI                      /* include pci support          */
 359 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 360 #define CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 361 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 362 #define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 363
 364 /* Board-specific PCI */
 365 #define CONFIG_SYS_PCI_TARGET_INIT
 366 #define CONFIG_SYS_PCI_MASTER_INIT
 367
 368 /*
 369  * For booting Linux, the board info and command line data
 370  * have to be in the first 8 MB of memory, since this is
 371  * the maximum mapped by the Linux kernel during initialization.
 372  */
 373 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)     /* Initial Memory map for Linux */
 374
 375 /*
 376  * External Bus Controller (EBC) Setup
 377  */
 378 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 379
 380 #define CONFIG_SYS_CPLD_BASE            0xC0000000
 381 #define CONFIG_SYS_CPLD_RANGE           0x00000010
 382 #define CONFIG_SYS_DUMEM_BASE           0xC0100000
 383 #define CONFIG_SYS_DUMEM_RANGE          0x00100000
 384 #define CONFIG_SYS_DUIO_BASE            0xC0200000
 385 #define CONFIG_SYS_DUIO_RANGE           0x00010000
 386
 387 #define CONFIG_SYS_NAND0_CS             2               /* NAND chip connected to CSx */
 388 #define CONFIG_SYS_NAND1_CS             3               /* NAND chip connected to CSx */
 389 /* Memory Bank 0 (NOR-FLASH) initialization */
 390 #define CONFIG_SYS_EBC_PB0AP            0x04017200
 391 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 392
 393 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
 394 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
 395 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 396
 397 /* Memory Bank 2 (NAND-FLASH) initialization */
 398 #define CONFIG_SYS_EBC_PB2AP            0x018003c0
 399 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND0_ADDR | 0x1c000)
 400
 401 /* Memory Bank 3 (NAND-FLASH) initialization */
 402 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 403 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND1_ADDR | 0x1c000)
 404
 405 /* Memory Bank 4 (DUMEM, 1MB) initialization */
 406 #define CONFIG_SYS_EBC_PB4AP            0x018053c0
 407 #define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_DUMEM_BASE | 0x18000)
 408
 409 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
 410 #define CONFIG_SYS_EBC_PB5AP            0x018053c0
 411 #define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_DUIO_BASE | 0x18000)
 412
 413 /*
 414  * NAND FLASH
 415  */
 416 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 417 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 418 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
 419                                  CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
 420
 421 #if defined(CONFIG_CMD_KGDB)
 422 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 423 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 424 #endif
 425
 426 #define CONFIG_SOURCE           1
 427
 428 #define CONFIG_OF_LIBFDT
 429 #define CONFIG_OF_BOARD_SETUP
 430
 431 #endif  /* __CONFIG_H */