include/configs/DU440.h

   1 /*
   2  * (C) Copyright 2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * based on the Sequoia board configuration by
   6  * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  **********************************************************************
  26  * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
  27  **********************************************************************
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_DU440            1               /* Board is esd DU440   */
  36 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  37 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  38 #define CONFIG_SYS_CLK_FREQ     33333400        /* external freq to pll */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  41 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  42 #define CONFIG_LAST_STAGE_INIT  1               /* last_stage_init      */
  43
  44 /*
  45  * Base addresses -- Note these are effective addresses where the
  46  * actual resources get mapped (not physical addresses)
  47  */
  48 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384 kB for Monitor */
  49 #define CONFIG_SYS_MALLOC_LEN           (8 << 20)       /* Reserve 8 MB for malloc()  */
  50
  51 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  52 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  53 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  54 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  55 #define CONFIG_SYS_NAND0_ADDR           0xd0000000      /* NAND Flash           */
  56 #define CONFIG_SYS_NAND1_ADDR           0xd0100000      /* NAND Flash           */
  57 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  58 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  59 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  60 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  61 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  62 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  63 #define CONFIG_SYS_PCI_IOBASE          0xe8000000
  64
  65
  66 /* Don't change either of these */
  67 #define CONFIG_SYS_PERIPHERAL_BASE      0xef600000      /* internal peripherals */
  68
  69 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  70 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  71 #define CONFIG_SYS_USB_HOST             0xe0000400
  72
  73 /*
  74  * Initial RAM & stack pointer
  75  */
  76 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  77 #define CONFIG_SYS_INIT_RAM_OCM 1               /* OCM as init ram      */
  78 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  79
  80 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
  81 #define CONFIG_SYS_GBL_DATA_SIZE        256             /* num bytes initial data */
  82 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  83 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  84
  85 /*
  86  * Serial Port
  87  */
  88 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  89 #define CONFIG_BAUDRATE         115200
  90 #define CONFIG_SERIAL_MULTI     1
  91 #undef CONFIG_UART1_CONSOLE
  92
  93 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
  94         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  95
  96 /*
  97  * Video Port
  98  */
  99 #define CONFIG_VIDEO
 100 #define CONFIG_VIDEO_SMI_LYNXEM
 101 #define CONFIG_CFB_CONSOLE
 102 #define CONFIG_VIDEO_LOGO
 103 #define CONFIG_VGA_AS_SINGLE_DEVICE
 104 #define CONFIG_SPLASH_SCREEN
 105 #define CONFIG_SPLASH_SCREEN_ALIGN
 106 #define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
 107 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
 108 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
 109 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 110 #define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
 111
 112 /*
 113  * Environment
 114  */
 115 #define CONFIG_ENV_IS_IN_EEPROM    1    /* use FLASH for environment vars */
 116
 117 /*
 118  * FLASH related
 119  */
 120 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible */
 121 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver       */
 122
 123 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 124
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 126 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 127
 128 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 129 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 130
 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 132 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
 133 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 134
 135 #define CONFIG_SYS_FLASH_EMPTY_INFO
 136 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 137
 138 #ifdef CONFIG_ENV_IS_IN_FLASH
 139 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 140 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 141 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 142
 143 /* Address and size of Redundant Environment Sector     */
 144 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 145 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 146 #endif
 147
 148 #ifdef CONFIG_ENV_IS_IN_EEPROM
 149 #define CONFIG_ENV_OFFSET               0       /* environment starts at */
 150                                         /* the beginning of the EEPROM */
 151 #define CONFIG_ENV_SIZE         0x1000 /* 4096 bytes may be used for env vars */
 152 #endif
 153
 154 /*
 155  * DDR SDRAM
 156  */
 157 #define CONFIG_SYS_MBYTES_SDRAM        (1024)   /* 512 MiB      TODO: remove    */
 158 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 159 #define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
 160                                         /* 440EPx errata CHIP 11        */
 161 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 162 #define CONFIG_DDR_ECC                  /* Use ECC when available       */
 163 #define SPD_EEPROM_ADDRESS      {0x50}
 164 #define CONFIG_PROG_SDRAM_TLB
 165
 166 /*
 167  * I2C
 168  */
 169 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 170 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 171 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 172 #define CONFIG_SYS_I2C_SLAVE            0x7F
 173 #define CONFIG_I2C_CMD_TREE     1
 174 #define CONFIG_I2C_MULTI_BUS    1
 175
 176 #define CONFIG_SYS_SPD_BUS_NUM         0
 177 #define IIC1_MCP3021_ADDR       0x4d
 178 #define IIC1_USB2507_ADDR       0x2c
 179 #ifdef CONFIG_I2C_MULTI_BUS
 180 #define CONFIG_SYS_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
 181 #endif
 182 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54
 184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
 186 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 187 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
 188
 189 #define CONFIG_SYS_EEPROM_WREN         1
 190 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 191
 192 /*
 193  * standard dtt sensor configuration - bottom bit will determine local or
 194  * remote sensor of the TMP401
 195  */
 196 #define CONFIG_DTT_SENSORS              { 0, 1 }
 197
 198 /*
 199  * The PMC440 uses a TI TMP401 temperature sensor. This part
 200  * is basically compatible to the ADM1021 that is supported
 201  * by U-Boot.
 202  *
 203  * - i2c addr 0x4c
 204  * - conversion rate 0x02 = 0.25 conversions/second
 205  * - ALERT ouput disabled
 206  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 207  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 208  */
 209 #define CONFIG_DTT_ADM1021
 210 #define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 211
 212 /*
 213  * RTC stuff
 214  */
 215 #define CONFIG_RTC_DS1338
 216 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 217
 218 #undef  CONFIG_BOOTARGS
 219
 220 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 221         "netdev=eth0\0"                                                 \
 222         "ethrotate=no\0"                                                \
 223         "hostname=du440\0"                                              \
 224         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 225                 "nfsroot=${serverip}:${rootpath}\0"                     \
 226         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 227         "addip=setenv bootargs ${bootargs} "                            \
 228                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 229                 ":${hostname}:${netdev}:off panic=1\0"                  \
 230         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 231         "flash_self=run ramargs addip addtty optargs;"                  \
 232                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 233         "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;"  \
 234                 "bootm\0"                                               \
 235         "rootpath=/tftpboot/du440/target_root_du440\0"                  \
 236         "img=/tftpboot/du440/uImage\0"                                  \
 237         "kernel_addr=FFC00000\0"                                        \
 238         "ramdisk_addr=FFE00000\0"                                       \
 239         "initrd_high=30000000\0"                                        \
 240         "load=tftp 100000 /tftpboot/du440/u-boot.bin\0"                 \
 241         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 242                 "cp.b 100000 FFFA0000 60000\0"                          \
 243         ""
 244
 245 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 246
 247 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds     */
 248
 249 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 250 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 251
 252 #ifndef __ASSEMBLY__
 253 int du440_phy_addr(int devnum);
 254 #endif
 255
 256 #define CONFIG_IBM_EMAC4_V4     1
 257 #define CONFIG_MII              1       /* MII PHY management           */
 258 #define CONFIG_PHY_ADDR         du440_phy_addr(0) /* PHY address        */
 259
 260 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 261 #undef CONFIG_PHY_GIGE                  /* no GbE detection             */
 262
 263 #define CONFIG_HAS_ETH0
 264 #define CONFIG_SYS_RX_ETH_BUFFER        128
 265
 266 #define CONFIG_NET_MULTI        1
 267 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 268 #define CONFIG_PHY1_ADDR        du440_phy_addr(1)
 269
 270 /*
 271  * USB
 272  */
 273 #define CONFIG_USB_OHCI_NEW
 274 #define CONFIG_USB_STORAGE
 275 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 276
 277 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 278 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 279 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "du440"
 280 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 281
 282 /* Comment this out to enable USB 1.1 device */
 283 #define USB_2_0_DEVICE
 284
 285 /* Partitions */
 286 #define CONFIG_MAC_PARTITION
 287 #define CONFIG_DOS_PARTITION
 288 #define CONFIG_ISO_PARTITION
 289
 290 #include <config_cmd_default.h>
 291
 292 #define CONFIG_CMD_AUTOSCRIPT
 293 #define CONFIG_CMD_BSP
 294 #define CONFIG_CMD_BMP
 295 #define CONFIG_CMD_DATE
 296 #define CONFIG_CMD_ASKENV
 297 #define CONFIG_CMD_DHCP
 298 #define CONFIG_CMD_DTT
 299 #define CONFIG_CMD_DIAG
 300 #define CONFIG_CMD_EEPROM
 301 #define CONFIG_CMD_ELF
 302 #define CONFIG_CMD_FAT
 303 #define CONFIG_CMD_I2C
 304 #define CONFIG_CMD_IRQ
 305 #define CONFIG_CMD_MII
 306 #define CONFIG_CMD_NAND
 307 #define CONFIG_CMD_NET
 308 #define CONFIG_CMD_NFS
 309 #define CONFIG_CMD_PCI
 310 #define CONFIG_CMD_PING
 311 #define CONFIG_CMD_USB
 312 #define CONFIG_CMD_REGINFO
 313 #define CONFIG_CMD_SDRAM
 314
 315 #define CONFIG_SUPPORT_VFAT
 316
 317 /*
 318  * Miscellaneous configurable options
 319  */
 320 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 321 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 322 #if defined(CONFIG_CMD_KGDB)
 323 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 324 #else
 325 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 326 #endif
 327 /* Print Buffer Size */
 328 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 329 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 330 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 331
 332 #define CONFIG_SYS_MEMTEST_START        0x00400000 /* memtest works on          */
 333 #define CONFIG_SYS_MEMTEST_END          0x3f000000 /* 4 ... < 1GB DRAM  */
 334
 335 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 336 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 337
 338 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 339
 340 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 341 #define CONFIG_LOOPW            1       /* enable loopw command         */
 342 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 343 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 344 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 345
 346 #define CONFIG_AUTOBOOT_KEYED   1
 347 #define CONFIG_AUTOBOOT_PROMPT  \
 348         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 349 #define CONFIG_AUTOBOOT_DELAY_STR "d"
 350 #define CONFIG_AUTOBOOT_STOP_STR " "
 351
 352 /*
 353  * PCI stuff
 354  */
 355 #define CONFIG_PCI                      /* include pci support          */
 356 #define CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 357 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 358 #define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 359
 360 /* Board-specific PCI */
 361 #define CONFIG_SYS_PCI_TARGET_INIT
 362 #define CONFIG_SYS_PCI_MASTER_INIT
 363
 364 /*
 365  * For booting Linux, the board info and command line data
 366  * have to be in the first 8 MB of memory, since this is
 367  * the maximum mapped by the Linux kernel during initialization.
 368  */
 369 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)     /* Initial Memory map for Linux */
 370
 371 /*
 372  * External Bus Controller (EBC) Setup
 373  */
 374 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 375
 376 #define CONFIG_SYS_CPLD_BASE            0xC0000000
 377 #define CONFIG_SYS_CPLD_RANGE           0x00000010
 378 #define CONFIG_SYS_DUMEM_BASE           0xC0100000
 379 #define CONFIG_SYS_DUMEM_RANGE          0x00100000
 380 #define CONFIG_SYS_DUIO_BASE            0xC0200000
 381 #define CONFIG_SYS_DUIO_RANGE           0x00010000
 382
 383 #define CONFIG_SYS_NAND0_CS             2               /* NAND chip connected to CSx */
 384 #define CONFIG_SYS_NAND1_CS             3               /* NAND chip connected to CSx */
 385 /* Memory Bank 0 (NOR-FLASH) initialization */
 386 #define CONFIG_SYS_EBC_PB0AP            0x04017200
 387 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 388
 389 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
 390 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
 391 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 392
 393 /* Memory Bank 2 (NAND-FLASH) initialization */
 394 #define CONFIG_SYS_EBC_PB2AP            0x018003c0
 395 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND0_ADDR | 0x1c000)
 396
 397 /* Memory Bank 3 (NAND-FLASH) initialization */
 398 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 399 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND1_ADDR | 0x1c000)
 400
 401 /* Memory Bank 4 (DUMEM, 1MB) initialization */
 402 #define CONFIG_SYS_EBC_PB4AP            0x018053c0
 403 #define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_DUMEM_BASE | 0x18000)
 404
 405 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
 406 #define CONFIG_SYS_EBC_PB5AP            0x018053c0
 407 #define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_DUIO_BASE | 0x18000)
 408
 409 /*
 410  * NAND FLASH
 411  */
 412 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 413 #define NAND_MAX_CHIPS          CONFIG_SYS_MAX_NAND_DEVICE
 414 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 415 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
 416                                  CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
 417
 418 /*
 419  * Internal Definitions
 420  *
 421  * Boot Flags
 422  */
 423 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 424 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 425
 426 #if defined(CONFIG_CMD_KGDB)
 427 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 428 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 429 #endif
 430
 431 #define CONFIG_AUTOSCRIPT       1
 432
 433 #define CONFIG_OF_LIBFDT
 434 #define CONFIG_OF_BOARD_SETUP
 435
 436 #endif  /* __CONFIG_H */