include/configs/EB+MCF-EV123.h

   1 /*
   2  * Configuation settings for the BuS EB+MCF-EV123 boards.
   3  *
   4  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef _CONFIG_EB_MCF_EV123_H_
  26 #define _CONFIG_EB_MCF_EV123_H_
  27
  28 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  29
  30 /*----------------------------------------------------------------------*
  31  * High Level Configuration Options (easy to change)                    *
  32  *----------------------------------------------------------------------*/
  33
  34 #define CONFIG_MCF52x2                  /* define processor family */
  35 #define CONFIG_M5282                    /* define processor type */
  36 #define CONFIG_EB_MCF_EV123
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define CONFIG_MCFUART
  41 #define CONFIG_SYS_UART_PORT            (0)
  42 #define CONFIG_BAUDRATE 9600
  43 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  44
  45 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  46
  47 #define CONFIG_BOOTCOMMAND "printenv"
  48
  49 /*----------------------------------------------------------------------*
  50  * Options                                                              *
  51  *----------------------------------------------------------------------*/
  52
  53 #define CONFIG_BOOT_RETRY_TIME  -1
  54 #define CONFIG_RESET_TO_RETRY
  55 #define CONFIG_SPLASH_SCREEN
  56
  57 /*----------------------------------------------------------------------*
  58  * Configuration for environment                                        *
  59  * Environment is in the second sector of the first 256k of flash       *
  60  *----------------------------------------------------------------------*/
  61
  62 #ifndef CONFIG_MONITOR_IS_IN_RAM
  63 #define CONFIG_ENV_ADDR         0xF003C000      /* End of 256K */
  64 #define CONFIG_ENV_SECT_SIZE    0x4000
  65 #define CONFIG_ENV_IS_IN_FLASH  1
  66 #else
  67 #define CONFIG_ENV_ADDR         0xFFE04000
  68 #define CONFIG_ENV_SECT_SIZE    0x2000
  69 #define CONFIG_ENV_IS_IN_FLASH  1
  70 #endif
  71
  72 /*
  73  * BOOTP options
  74  */
  75 #define CONFIG_BOOTP_BOOTFILESIZE
  76 #define CONFIG_BOOTP_BOOTPATH
  77 #define CONFIG_BOOTP_GATEWAY
  78 #define CONFIG_BOOTP_HOSTNAME
  79
  80 /*
  81  * Command line configuration.
  82  */
  83 #include <config_cmd_default.h>
  84
  85 #undef CONFIG_CMD_LOADB
  86 #define CONFIG_CMD_MII
  87 #define CONFIG_CMD_NET
  88
  89 #define CONFIG_MCFTMR
  90
  91
  92 #define CONFIG_BOOTDELAY        5
  93 #define CONFIG_HUSH_PARSER
  94 #define CONFIG_SYS_PROMPT       "\nEV123 U-Boot> "
  95 #define CONFIG_SYS_LONGHELP     1
  96
  97 #if defined(CONFIG_CMD_KGDB)
  98 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  99 #else
 100 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size      */
 101 #endif
 102 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 103 #define CONFIG_SYS_MAXARGS      16      /* max number of command args   */
 104 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 105
 106 #define CONFIG_SYS_LOAD_ADDR            0x20000
 107
 108 #define CONFIG_SYS_MEMTEST_START        0x100000
 109 #define CONFIG_SYS_MEMTEST_END          0x400000
 110 /*#define CONFIG_SYS_DRAM_TEST          1 */
 111 #undef CONFIG_SYS_DRAM_TEST
 112
 113 /*----------------------------------------------------------------------*
 114  * Clock and PLL Configuration                                          *
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_HZ                   10000000
 117 #define CONFIG_SYS_CLK                  58982400       /* 9,8304MHz * 6 */
 118
 119 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
 120
 121 #define CONFIG_SYS_MFD          0x01    /* PLL Multiplication Factor Devider */
 122 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
 123
 124 /*----------------------------------------------------------------------*
 125  * Network                                                              *
 126  *----------------------------------------------------------------------*/
 127
 128 #define CONFIG_MCFFEC
 129 #define CONFIG_NET_MULTI                1
 130 #define CONFIG_MII                      1
 131 #define CONFIG_MII_INIT                 1
 132 #define CONFIG_SYS_DISCOVER_PHY
 133 #define CONFIG_SYS_RX_ETH_BUFFER        8
 134 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 135
 136 #define CONFIG_SYS_FEC0_PINMUX          0
 137 #define CONFIG_SYS_FEC0_MIIBASE         CONFIG_SYS_FEC0_IOBASE
 138 #define MCFFEC_TOUT_LOOP                50000
 139
 140 #define CONFIG_ETHADDR                  00:CF:52:82:EB:01
 141 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 142
 143 /*-------------------------------------------------------------------------
 144  * Low Level Configuration Settings
 145  * (address mappings, register initial values, etc.)
 146  * You should know what you are doing if you make changes here.
 147  *-----------------------------------------------------------------------*/
 148
 149 #define CONFIG_SYS_MBAR                 0x40000000
 150
 151 /*-----------------------------------------------------------------------
 152  * Definitions for initial stack pointer and data area (in DPRAM)
 153  *-----------------------------------------------------------------------*/
 154
 155 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 156 #define CONFIG_SYS_INIT_RAM_SIZE                0x10000
 157 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 158         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 159 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 160
 161 /*-----------------------------------------------------------------------
 162  * Start addresses for the final memory configuration
 163  * (Set up by the startup code)
 164  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 165  */
 166 #define CONFIG_SYS_SDRAM_BASE1          0x00000000
 167 #define CONFIG_SYS_SDRAM_SIZE1          16      /* SDRAM size in MB */
 168
 169 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE1
 170 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE1
 171
 172
 173 /* If M5282 port is fully implemented the monitor base will be behind
 174  * the vector table. */
 175 #if (CONFIG_SYS_TEXT_BASE !=  CONFIG_SYS_INT_FLASH_BASE)
 176 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
 177 #else
 178 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
 179 #endif
 180
 181 #define CONFIG_SYS_MONITOR_LEN          0x20000
 182 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 183 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 184
 185 /*
 186  * For booting Linux, the board info and command line data
 187  * have to be in the first 8 MB of memory, since this is
 188  * the maximum mapped by the Linux kernel during initialization ??
 189  */
 190 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 191
 192 /*-----------------------------------------------------------------------
 193  * FLASH organization
 194  */
 195
 196 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 197 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 198 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 199
 200 #define CONFIG_SYS_MAX_FLASH_SECT       35
 201 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 202 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 203 #define CONFIG_SYS_FLASH_PROTECTION
 204
 205 /*-----------------------------------------------------------------------
 206  * Cache Configuration
 207  */
 208 #define CONFIG_SYS_CACHELINE_SIZE       16
 209
 210 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 211                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 212 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 213                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 214 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 215 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 216                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 217                                          CF_ACR_EN | CF_ACR_SM_ALL)
 218 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 219                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 220                                          CF_CACR_EUSP)
 221
 222 /*-----------------------------------------------------------------------
 223  * Memory bank definitions
 224  */
 225
 226 #define CONFIG_SYS_CS0_BASE             0xFFE00000
 227 #define CONFIG_SYS_CS0_CTRL             0x00001980
 228 #define CONFIG_SYS_CS0_MASK             0x001F0001
 229
 230 #define CONFIG_SYS_CS3_BASE             0xE0000000
 231 #define CONFIG_SYS_CS0_CTRL             0x00001980
 232 #define CONFIG_SYS_CS3_MASK             0x000F0001
 233
 234 /*-----------------------------------------------------------------------
 235  * Port configuration
 236  */
 237 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 238 #define CONFIG_SYS_PADDR                0x0000000
 239 #define CONFIG_SYS_PADAT                0x0000000
 240
 241 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 242 #define CONFIG_SYS_PBDDR                0x0000000
 243 #define CONFIG_SYS_PBDAT                0x0000000
 244
 245 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 246 #define CONFIG_SYS_PCDDR                0x0000000
 247 #define CONFIG_SYS_PCDAT                0x0000000
 248
 249 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 250 #define CONFIG_SYS_PCDDR                0x0000000
 251 #define CONFIG_SYS_PCDAT                0x0000000
 252
 253 #define CONFIG_SYS_PEHLPAR              0xC0
 254 #define CONFIG_SYS_PUAPAR               0x0F
 255 #define CONFIG_SYS_DDRUA                0x05
 256 #define CONFIG_SYS_PJPAR                0xFF
 257
 258 /*-----------------------------------------------------------------------
 259  * VIDEO configuration
 260  */
 261
 262 #define CONFIG_VIDEO
 263
 264 #ifdef CONFIG_VIDEO
 265 #define CONFIG_VIDEO_VCXK                       1
 266
 267 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 268 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 269 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS3_BASE
 270 #define CONFIG_SYS_VCXK_AUTODETECT              1
 271
 272 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 273 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 274 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 275
 276 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 277 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 278 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 279
 280 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 281 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 282 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 283
 284 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 285 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 286 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 287
 288 #endif /* CONFIG_VIDEO */
 289 #endif  /* _CONFIG_M5282EVB_H */
 290 /*---------------------------------------------------------------------*/