include/configs/ELPT860.h

   1 /*
   2 **=====================================================================
   3 **
   4 ** Copyright (C) 2000, 2001, 2002, 2003
   5 ** The LEOX team <team@leox.org>, http://www.leox.org
   6 **
   7 ** LEOX.org is about the development of free hardware and software resources
   8 **   for system on chip.
   9 **
  10 ** Description: U-Boot port on the LEOX's ELPT860 CPU board
  11 ** ~~~~~~~~~~~
  12 **
  13 **=====================================================================
  14 **
  15 ** This program is free software; you can redistribute it and/or
  16 ** modify it under the terms of the GNU General Public License as
  17 ** published by the Free Software Foundation; either version 2 of
  18 ** the License, or (at your option) any later version.
  19 **
  20 ** This program is distributed in the hope that it will be useful,
  21 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 ** GNU General Public License for more details.
  24 **
  25 ** You should have received a copy of the GNU General Public License
  26 ** along with this program; if not, write to the Free Software
  27 ** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 ** MA 02111-1307 USA
  29 **
  30 **=====================================================================
  31 */
  32
  33 /*
  34  * board/config.h - configuration options, board specific
  35  */
  36
  37 #ifndef __CONFIG_H
  38 #define __CONFIG_H
  39
  40
  41 /*
  42  * High Level Configuration Options
  43  * (easy to change)
  44  */
  45
  46 #define CONFIG_MPC860           1       /* It's a MPC860, in fact a 860T CPU */
  47 #define CONFIG_MPC860T          1
  48 #define CONFIG_ELPT860          1       /* ...on a LEOX's ELPT860 CPU board */
  49
  50 #define CONFIG_SYS_TEXT_BASE    0x02000000
  51
  52 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1               */
  53 #undef    CONFIG_8xx_CONS_SMC2
  54 #undef    CONFIG_8xx_CONS_NONE
  55
  56 #define CONFIG_CLOCKS_IN_MHZ    1  /* Clock passed to Linux (<2.4.5) in MHz */
  57 #define CONFIG_8xx_GCLK_FREQ    50000000       /* MPC860T runs at 50MHz */
  58
  59 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  60
  61 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  62 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  63
  64 /* BOOT arguments */
  65 #define CONFIG_PREBOOT                                                     \
  66      "echo;"                                                               \
  67      "echo Type \"run nfsboot\" to mount root filesystem over NFS;"        \
  68      "echo"
  69
  70 #undef    CONFIG_BOOTARGS
  71
  72 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  73     "ramargs=setenv bootargs root=/dev/ram rw\0"                        \
  74     "rootargs=setenv rootpath /tftp/${ipaddr}\0"                        \
  75     "nfsargs=setenv bootargs root=/dev/nfs rw "                         \
  76         "nfsroot=${serverip}:${rootpath}\0"                             \
  77     "addip=setenv bootargs ${bootargs} "                                \
  78         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"              \
  79         ":${hostname}:eth0:off panic=1\0"                               \
  80     "ramboot=tftp 400000 /home/paugaml/pMulti;"                         \
  81         "run ramargs;bootm\0"                                           \
  82     "nfsboot=tftp 400000 /home/paugaml/uImage;"                         \
  83         "run rootargs;run nfsargs;run addip;bootm\0"                    \
  84     ""
  85 #define CONFIG_BOOTCOMMAND      "run ramboot"
  86
  87 /*
  88  * BOOTP options
  89  */
  90 #define CONFIG_BOOTP_SUBNETMASK
  91 #define CONFIG_BOOTP_GATEWAY
  92 #define CONFIG_BOOTP_HOSTNAME
  93 #define CONFIG_BOOTP_BOOTPATH
  94 #define CONFIG_BOOTP_BOOTFILESIZE
  95
  96
  97 #undef    CONFIG_WATCHDOG               /* watchdog disabled            */
  98 #undef    CONFIG_CAN_DRIVER             /* CAN Driver support disabled  */
  99 #undef    CONFIG_RTC_MPC8xx             /* internal RTC MPC8xx unused   */
 100 #define CONFIG_RTC_DS164x       1       /* RTC is a Dallas DS1646       */
 101
 102 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 103 #undef    CONFIG_SYS_LOADS_BAUD_CHANGE          /* don't allow baudrate change  */
 104
 105
 106 /*
 107  * Command line configuration.
 108  */
 109 #include <config_cmd_default.h>
 110
 111 #define CONFIG_CMD_ASKENV
 112 #define CONFIG_CMD_DATE
 113
 114
 115 /*
 116  * Miscellaneous configurable options
 117  */
 118 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 119 #define CONFIG_SYS_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt        */
 120
 121 #if defined(CONFIG_CMD_KGDB)
 122 #  define CONFIG_SYS_CBSIZE     1024            /* Console I/O Buffer Size      */
 123 #else
 124 #  define CONFIG_SYS_CBSIZE      256            /* Console I/O Buffer Size      */
 125 #endif
 126
 127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 128 #define CONFIG_SYS_MAXARGS        16            /* max number of command args   */
 129 #define CONFIG_SYS_BARGSIZE       CONFIG_SYS_CBSIZE     /* Boot Argument Buffer Size    */
 130
 131 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 132 #define CONFIG_SYS_MEMTEST_END          0x00C00000      /* 4 ... 12 MB in DRAM  */
 133
 134 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 135
 136 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 137
 138 /*
 139  * Environment Variables and Storages
 140  */
 141 #define CONFIG_ENV_OVERWRITE    1  /* Allow Overwrite of serial# & ethaddr */
 142
 143 #undef    CONFIG_ENV_IS_IN_NVRAM               /* Environment is in NVRAM       */
 144 #undef    CONFIG_ENV_IS_IN_EEPROM              /* Environment is in I2C EEPROM  */
 145 #define CONFIG_ENV_IS_IN_FLASH  1      /* Environment is in FLASH       */
 146
 147 #define CONFIG_BAUDRATE         9600   /* console baudrate = 9600 bps   */
 148 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 149
 150 #define CONFIG_ETHADDR          00:01:77:00:60:40
 151 #define CONFIG_IPADDR           192.168.0.30
 152 #define CONFIG_NETMASK          255.255.255.0
 153
 154 #define CONFIG_SERVERIP         192.168.0.1
 155 #define CONFIG_GATEWAYIP        192.168.0.1
 156
 157 /*
 158  * Low Level Configuration Settings
 159  * (address mappings, register initial values, etc.)
 160  * You should know what you are doing if you make changes here.
 161  */
 162
 163 /*-----------------------------------------------------------------------
 164  * Internal Memory Mapped Register
 165  */
 166 #define CONFIG_SYS_IMMR         0xFF000000
 167
 168 /*-----------------------------------------------------------------------
 169  * Definitions for initial stack pointer and data area (in DPRAM)
 170  */
 171 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 172 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 173 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 174 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 175
 176 /*-----------------------------------------------------------------------
 177  * Start addresses for the final memory configuration
 178  * (Set up by the startup code)
 179  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 180  */
 181 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 182 #define CONFIG_SYS_FLASH_BASE           0x02000000
 183 #define CONFIG_SYS_NVRAM_BASE           0x03000000
 184
 185 #if defined(CONFIG_ENV_IS_IN_FLASH)
 186 #  if defined(DEBUG)
 187 #    define CONFIG_SYS_MONITOR_LEN      (320 << 10)  /* Reserve 320 kB for Monitor  */
 188 #  else
 189 #    define CONFIG_SYS_MONITOR_LEN      (256 << 10)  /* Reserve 256 kB for Monitor  */
 190 #  endif
 191 #else
 192 #  if defined(DEBUG)
 193 #    define CONFIG_SYS_MONITOR_LEN      (256 << 10)  /* Reserve 256 kB for Monitor  */
 194 #  else
 195 #    define CONFIG_SYS_MONITOR_LEN      (192 << 10)  /* Reserve 192 kB for Monitor  */
 196 #  endif
 197 #endif
 198
 199 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 200 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)  /* Reserve 128 kB for malloc() */
 201
 202 /*
 203  * For booting Linux, the board info and command line data
 204  * have to be in the first 8 MB of memory, since this is
 205  * the maximum mapped by the Linux kernel during initialization.
 206  */
 207 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)    /* Initial Memory map for Linux */
 208
 209 /*-----------------------------------------------------------------------
 210  * FLASH organization
 211  */
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks        */
 213 #define CONFIG_SYS_MAX_FLASH_SECT       8       /* max number of sectors on one chip */
 214
 215 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)   */
 216 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)   */
 217
 218 #if defined(CONFIG_ENV_IS_IN_FLASH)
 219 #  define CONFIG_ENV_OFFSET     0x10000 /* Offset   of Environment Sector    */
 220 #  define CONFIG_ENV_SIZE               0x10000 /* Total Size of Environment Sector  */
 221 #endif
 222
 223 /*-----------------------------------------------------------------------
 224  * NVRAM organization
 225  */
 226 #define CONFIG_SYS_NVRAM_BASE_ADDR      CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
 227 #define CONFIG_SYS_NVRAM_SIZE           ((128*1024)-8) /* clock regs resident in the */
 228                                                /*   8 top NVRAM locations    */
 229
 230 #if defined(CONFIG_ENV_IS_IN_NVRAM)
 231 #  define CONFIG_ENV_ADDR               CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
 232 #  define CONFIG_ENV_SIZE               0x4000  /* Total Size of Environment Sector  */
 233 #endif
 234
 235 /*-----------------------------------------------------------------------
 236  * Cache Configuration
 237  */
 238 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs               */
 239
 240 #if defined(CONFIG_CMD_KGDB)
 241 #  define CONFIG_SYS_CACHELINE_SHIFT     4      /* log base 2 of the above value     */
 242 #endif
 243
 244 /*-----------------------------------------------------------------------
 245  * SYPCR - System Protection Control                            11-9
 246  * SYPCR can only be written once after reset!
 247  *-----------------------------------------------------------------------
 248  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 249  */
 250 #if defined(CONFIG_WATCHDOG)
 251 #  define CONFIG_SYS_SYPCR      (SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
 252                          SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
 253 #else
 254 #  define CONFIG_SYS_SYPCR      (SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
 255                                                    SYPCR_SWP)
 256 #endif
 257
 258 /*-----------------------------------------------------------------------
 259  * SUMCR - SIU Module Configuration                             11-6
 260  *-----------------------------------------------------------------------
 261  * PCMCIA config., multi-function pin tri-state
 262  */
 263 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11)
 264
 265 /*-----------------------------------------------------------------------
 266  * TBSCR - Time Base Status and Control                         11-26
 267  *-----------------------------------------------------------------------
 268  * Clear Reference Interrupt Status, Timebase freezing enabled
 269  */
 270 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 271
 272 /*-----------------------------------------------------------------------
 273  * RTCSC - Real-Time Clock Status and Control Register          11-27
 274  *-----------------------------------------------------------------------
 275  * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
 276  *  enabled
 277  */
 278 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 279
 280 /*-----------------------------------------------------------------------
 281  * PISCR - Periodic Interrupt Status and Control                11-31
 282  *-----------------------------------------------------------------------
 283  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 284  */
 285 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 286
 287 /*-----------------------------------------------------------------------
 288  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 289  *-----------------------------------------------------------------------
 290  * Reset PLL lock status sticky bit, timer expired status bit and timer
 291  * interrupt status bit - leave PLL multiplication factor unchanged !
 292  */
 293 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 294
 295 /*-----------------------------------------------------------------------
 296  * SCCR - System Clock and reset Control Register               15-27
 297  *-----------------------------------------------------------------------
 298  * Set clock output, timebase and RTC source and divider,
 299  * power management and some other internal clocks
 300  */
 301 #define SCCR_MASK        SCCR_EBDF11
 302 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 303                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 304                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 305                          SCCR_DFALCD00)
 306
 307 /*-----------------------------------------------------------------------
 308  * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
 309  *-----------------------------------------------------------------------
 310  *
 311  */
 312 #ifdef DEBUG
 313 #  define CONFIG_SYS_DER                0xFFE7400F      /* Debug Enable Register */
 314 #else
 315 #  define CONFIG_SYS_DER                0
 316 #endif
 317
 318 /*
 319  * Init Memory Controller:
 320  * ~~~~~~~~~~~~~~~~~~~~~~
 321  *
 322  * BR0 and OR0 (FLASH)
 323  */
 324
 325 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0          */
 326
 327 /* used to re-map FLASH both when starting from SRAM or FLASH:
 328  * restrict access enough to keep SRAM working (if any)
 329  * but not too much to meddle with FLASH accesses
 330  */
 331 #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000      /* 16 MB between each CSx */
 332
 333 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0          */
 334 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
 335
 336 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 337 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 338
 339 /*
 340  * BR1 and OR1 (SDRAM)
 341  *
 342  */
 343 #define SDRAM_BASE1_PRELIM      CONFIG_SYS_SDRAM_BASE   /* SDRAM bank #0        */
 344 #define SDRAM_MAX_SIZE          0x02000000      /* 32 MB MAX for CS1    */
 345
 346 /* SDRAM timing:                                                        */
 347 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000000
 348
 349 #define CONFIG_SYS_OR1_PRELIM   ((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM )
 350 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 351
 352 /*
 353  * BR2 and OR2 (NVRAM)
 354  *
 355  */
 356 #define NVRAM_BASE1_PRELIM      CONFIG_SYS_NVRAM_BASE   /* NVRAM bank #0        */
 357 #define NVRAM_MAX_SIZE          0x00020000      /* 128 KB MAX for CS2   */
 358
 359 #define CONFIG_SYS_OR2_PRELIM           0xFFF80160
 360 #define CONFIG_SYS_BR2_PRELIM   ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 361
 362 /*
 363  * Memory Periodic Timer Prescaler
 364  */
 365
 366 /* periodic timer for refresh */
 367 #define CONFIG_SYS_MAMR_PTA             97     /* start with divider for 100 MHz */
 368
 369 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
 370 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16   /* setting for 2 banks */
 371 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32   /* setting for 1 bank  */
 372
 373 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit  */
 374 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8    /* setting for 2 banks */
 375 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16   /* setting for 1 bank  */
 376
 377 /*
 378  * MAMR settings for SDRAM
 379  */
 380
 381 /* 8 column SDRAM */
 382 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       | \
 383                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
 384                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 385 /* 9 column SDRAM */
 386 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       | \
 387                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
 388                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 389
 390 #endif  /* __CONFIG_H */