include/configs/ELPT860.h

   1 /*
   2 **=====================================================================
   3 **
   4 ** Copyright (C) 2000, 2001, 2002, 2003
   5 ** The LEOX team <team@leox.org>, http://www.leox.org
   6 **
   7 ** LEOX.org is about the development of free hardware and software resources
   8 **   for system on chip.
   9 **
  10 ** Description: U-Boot port on the LEOX's ELPT860 CPU board
  11 ** ~~~~~~~~~~~
  12 **
  13 **=====================================================================
  14 **
  15 ** This program is free software; you can redistribute it and/or
  16 ** modify it under the terms of the GNU General Public License as
  17 ** published by the Free Software Foundation; either version 2 of
  18 ** the License, or (at your option) any later version.
  19 **
  20 ** This program is distributed in the hope that it will be useful,
  21 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 ** GNU General Public License for more details.
  24 **
  25 ** You should have received a copy of the GNU General Public License
  26 ** along with this program; if not, write to the Free Software
  27 ** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28 ** MA 02111-1307 USA
  29 **
  30 **=====================================================================
  31 */
  32
  33 /*
  34  * board/config.h - configuration options, board specific
  35  */
  36
  37 #ifndef __CONFIG_H
  38 #define __CONFIG_H
  39
  40
  41 /*
  42  * High Level Configuration Options
  43  * (easy to change)
  44  */
  45
  46 #define CONFIG_MPC860           1       /* It's a MPC860, in fact a 860T CPU */
  47 #define CONFIG_MPC860T          1
  48 #define CONFIG_ELPT860          1       /* ...on a LEOX's ELPT860 CPU board */
  49
  50 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1               */
  51 #undef    CONFIG_8xx_CONS_SMC2
  52 #undef    CONFIG_8xx_CONS_NONE
  53
  54 #define CONFIG_CLOCKS_IN_MHZ    1  /* Clock passed to Linux (<2.4.5) in MHz */
  55 #define CONFIG_8xx_GCLK_FREQ    50000000       /* MPC860T runs at 50MHz */
  56
  57 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  58
  59 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  60
  61 /* BOOT arguments */
  62 #define CONFIG_PREBOOT                                                     \
  63      "echo;"                                                               \
  64      "echo Type \"run nfsboot\" to mount root filesystem over NFS;"        \
  65      "echo"
  66
  67 #undef    CONFIG_BOOTARGS
  68
  69 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  70     "ramargs=setenv bootargs root=/dev/ram rw\0"                        \
  71     "rootargs=setenv rootpath /tftp/${ipaddr}\0"                        \
  72     "nfsargs=setenv bootargs root=/dev/nfs rw "                         \
  73         "nfsroot=${serverip}:${rootpath}\0"                             \
  74     "addip=setenv bootargs ${bootargs} "                                \
  75         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"              \
  76         ":${hostname}:eth0:off panic=1\0"                               \
  77     "ramboot=tftp 400000 /home/paugaml/pMulti;"                         \
  78         "run ramargs;bootm\0"                                           \
  79     "nfsboot=tftp 400000 /home/paugaml/uImage;"                         \
  80         "run rootargs;run nfsargs;run addip;bootm\0"                    \
  81     ""
  82 #define CONFIG_BOOTCOMMAND      "run ramboot"
  83
  84 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  85
  86 #undef    CONFIG_WATCHDOG               /* watchdog disabled            */
  87 #undef    CONFIG_CAN_DRIVER             /* CAN Driver support disabled  */
  88 #undef    CONFIG_RTC_MPC8xx             /* internal RTC MPC8xx unused   */
  89 #define CONFIG_RTC_DS164x       1       /* RTC is a Dallas DS1646       */
  90
  91 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  92 #undef    CFG_LOADS_BAUD_CHANGE         /* don't allow baudrate change  */
  93
  94
  95 /*
  96  * Command line configuration.
  97  */
  98 #include <config_cmd_default.h>
  99
 100 #define CONFIG_CMD_ASKENV
 101 #define CONFIG_CMD_DATE
 102
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CFG_LONGHELP                    /* undef to save memory         */
 108 #define CFG_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt       */
 109
 110 #if defined(CONFIG_CMD_KGDB)
 111 #  define CFG_CBSIZE    1024            /* Console I/O Buffer Size      */
 112 #else
 113 #  define CFG_CBSIZE     256            /* Console I/O Buffer Size      */
 114 #endif
 115
 116 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 117 #define CFG_MAXARGS       16            /* max number of command args   */
 118 #define CFG_BARGSIZE      CFG_CBSIZE    /* Boot Argument Buffer Size    */
 119
 120 #define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
 121 #define CFG_MEMTEST_END         0x00C00000      /* 4 ... 12 MB in DRAM  */
 122
 123 #define CFG_LOAD_ADDR           0x00100000      /* default load address */
 124
 125 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 126
 127 /*
 128  * Environment Variables and Storages
 129  */
 130 #define CONFIG_ENV_OVERWRITE    1  /* Allow Overwrite of serial# & ethaddr */
 131
 132 #undef    CFG_ENV_IS_IN_NVRAM          /* Environment is in NVRAM       */
 133 #undef    CFG_ENV_IS_IN_EEPROM         /* Environment is in I2C EEPROM  */
 134 #define CFG_ENV_IS_IN_FLASH     1      /* Environment is in FLASH       */
 135
 136 #define CONFIG_BAUDRATE         9600   /* console baudrate = 9600 bps   */
 137 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 138
 139 #define CONFIG_ETHADDR          00:01:77:00:60:40
 140 #define CONFIG_IPADDR           192.168.0.30
 141 #define CONFIG_NETMASK          255.255.255.0
 142
 143 #define CONFIG_SERVERIP         192.168.0.1
 144 #define CONFIG_GATEWAYIP        192.168.0.1
 145
 146 /*
 147  * Low Level Configuration Settings
 148  * (address mappings, register initial values, etc.)
 149  * You should know what you are doing if you make changes here.
 150  */
 151
 152 /*-----------------------------------------------------------------------
 153  * Internal Memory Mapped Register
 154  */
 155 #define CFG_IMMR                0xFF000000
 156
 157 /*-----------------------------------------------------------------------
 158  * Definitions for initial stack pointer and data area (in DPRAM)
 159  */
 160 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 161 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 162 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 163 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 164 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 165
 166 /*-----------------------------------------------------------------------
 167  * Start addresses for the final memory configuration
 168  * (Set up by the startup code)
 169  * Please note that CFG_SDRAM_BASE _must_ start at 0
 170  */
 171 #define CFG_SDRAM_BASE          0x00000000
 172 #define CFG_FLASH_BASE          0x02000000
 173 #define CFG_NVRAM_BASE          0x03000000
 174
 175 #if defined(CFG_ENV_IS_IN_FLASH)
 176 #  if defined(DEBUG)
 177 #    define CFG_MONITOR_LEN     (320 << 10)  /* Reserve 320 kB for Monitor  */
 178 #  else
 179 #    define CFG_MONITOR_LEN     (256 << 10)  /* Reserve 256 kB for Monitor  */
 180 #  endif
 181 #else
 182 #  if defined(DEBUG)
 183 #    define CFG_MONITOR_LEN     (256 << 10)  /* Reserve 256 kB for Monitor  */
 184 #  else
 185 #    define CFG_MONITOR_LEN     (192 << 10)  /* Reserve 192 kB for Monitor  */
 186 #  endif
 187 #endif
 188
 189 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 190 #define CFG_MALLOC_LEN          (128 << 10)  /* Reserve 128 kB for malloc() */
 191
 192 /*
 193  * For booting Linux, the board info and command line data
 194  * have to be in the first 8 MB of memory, since this is
 195  * the maximum mapped by the Linux kernel during initialization.
 196  */
 197 #define CFG_BOOTMAPSZ           (8 << 20)    /* Initial Memory map for Linux */
 198
 199 /*-----------------------------------------------------------------------
 200  * FLASH organization
 201  */
 202 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks        */
 203 #define CFG_MAX_FLASH_SECT      8       /* max number of sectors on one chip */
 204
 205 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
 206 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */
 207
 208 #if defined(CFG_ENV_IS_IN_FLASH)
 209 #  define CFG_ENV_OFFSET        0x10000 /* Offset   of Environment Sector    */
 210 #  define CFG_ENV_SIZE          0x10000 /* Total Size of Environment Sector  */
 211 #endif
 212
 213 /*-----------------------------------------------------------------------
 214  * NVRAM organization
 215  */
 216 #define CFG_NVRAM_BASE_ADDR     CFG_NVRAM_BASE /* Base address of NVRAM area */
 217 #define CFG_NVRAM_SIZE          ((128*1024)-8) /* clock regs resident in the */
 218                                                /*   8 top NVRAM locations    */
 219
 220 #if defined(CFG_ENV_IS_IN_NVRAM)
 221 #  define CFG_ENV_ADDR          CFG_NVRAM_BASE /* Base address of NVRAM area */
 222 #  define CFG_ENV_SIZE          0x4000  /* Total Size of Environment Sector  */
 223 #endif
 224
 225 /*-----------------------------------------------------------------------
 226  * Cache Configuration
 227  */
 228 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs               */
 229
 230 #if defined(CONFIG_CMD_KGDB)
 231 #  define CFG_CACHELINE_SHIFT    4      /* log base 2 of the above value     */
 232 #endif
 233
 234 /*-----------------------------------------------------------------------
 235  * SYPCR - System Protection Control                            11-9
 236  * SYPCR can only be written once after reset!
 237  *-----------------------------------------------------------------------
 238  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 239  */
 240 #if defined(CONFIG_WATCHDOG)
 241 #  define CFG_SYPCR     (SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
 242                          SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
 243 #else
 244 #  define CFG_SYPCR     (SYPCR_SWTC | SYPCR_BMT  | SYPCR_BME | SYPCR_SWF | \
 245                                                    SYPCR_SWP)
 246 #endif
 247
 248 /*-----------------------------------------------------------------------
 249  * SUMCR - SIU Module Configuration                             11-6
 250  *-----------------------------------------------------------------------
 251  * PCMCIA config., multi-function pin tri-state
 252  */
 253 #define CFG_SIUMCR      (SIUMCR_DBGC11)
 254
 255 /*-----------------------------------------------------------------------
 256  * TBSCR - Time Base Status and Control                         11-26
 257  *-----------------------------------------------------------------------
 258  * Clear Reference Interrupt Status, Timebase freezing enabled
 259  */
 260 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 261
 262 /*-----------------------------------------------------------------------
 263  * RTCSC - Real-Time Clock Status and Control Register          11-27
 264  *-----------------------------------------------------------------------
 265  * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
 266  *  enabled
 267  */
 268 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 269
 270 /*-----------------------------------------------------------------------
 271  * PISCR - Periodic Interrupt Status and Control                11-31
 272  *-----------------------------------------------------------------------
 273  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 274  */
 275 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 276
 277 /*-----------------------------------------------------------------------
 278  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 279  *-----------------------------------------------------------------------
 280  * Reset PLL lock status sticky bit, timer expired status bit and timer
 281  * interrupt status bit - leave PLL multiplication factor unchanged !
 282  */
 283 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 284
 285 /*-----------------------------------------------------------------------
 286  * SCCR - System Clock and reset Control Register               15-27
 287  *-----------------------------------------------------------------------
 288  * Set clock output, timebase and RTC source and divider,
 289  * power management and some other internal clocks
 290  */
 291 #define SCCR_MASK        SCCR_EBDF11
 292 #define CFG_SCCR        (SCCR_TBS     | \
 293                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 294                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 295                          SCCR_DFALCD00)
 296
 297 /*-----------------------------------------------------------------------
 298  * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
 299  *-----------------------------------------------------------------------
 300  *
 301  */
 302 #ifdef DEBUG
 303 #  define CFG_DER               0xFFE7400F      /* Debug Enable Register */
 304 #else
 305 #  define CFG_DER               0
 306 #endif
 307
 308 /*
 309  * Init Memory Controller:
 310  * ~~~~~~~~~~~~~~~~~~~~~~
 311  *
 312  * BR0 and OR0 (FLASH)
 313  */
 314
 315 #define FLASH_BASE0_PRELIM      CFG_FLASH_BASE  /* FLASH bank #0          */
 316
 317 /* used to re-map FLASH both when starting from SRAM or FLASH:
 318  * restrict access enough to keep SRAM working (if any)
 319  * but not too much to meddle with FLASH accesses
 320  */
 321 #define CFG_PRELIM_OR_AM        0xFF000000      /* 16 MB between each CSx */
 322
 323 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0          */
 324 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
 325
 326 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 327 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 328
 329 /*
 330  * BR1 and OR1 (SDRAM)
 331  *
 332  */
 333 #define SDRAM_BASE1_PRELIM      CFG_SDRAM_BASE  /* SDRAM bank #0        */
 334 #define SDRAM_MAX_SIZE          0x02000000      /* 32 MB MAX for CS1    */
 335
 336 /* SDRAM timing:                                                        */
 337 #define CFG_OR_TIMING_SDRAM     0x00000000
 338
 339 #define CFG_OR1_PRELIM  ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
 340 #define CFG_BR1_PRELIM  ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 341
 342 /*
 343  * BR2 and OR2 (NVRAM)
 344  *
 345  */
 346 #define NVRAM_BASE1_PRELIM      CFG_NVRAM_BASE  /* NVRAM bank #0        */
 347 #define NVRAM_MAX_SIZE          0x00020000      /* 128 KB MAX for CS2   */
 348
 349 #define CFG_OR2_PRELIM          0xFFF80160
 350 #define CFG_BR2_PRELIM  ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
 351
 352 /*
 353  * Memory Periodic Timer Prescaler
 354  */
 355
 356 /* periodic timer for refresh */
 357 #define CFG_MAMR_PTA            97     /* start with divider for 100 MHz */
 358
 359 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
 360 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16   /* setting for 2 banks */
 361 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32   /* setting for 1 bank  */
 362
 363 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit  */
 364 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8    /* setting for 2 banks */
 365 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16   /* setting for 1 bank  */
 366
 367 /*
 368  * MAMR settings for SDRAM
 369  */
 370
 371 /* 8 column SDRAM */
 372 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      | \
 373                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
 374                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 375 /* 9 column SDRAM */
 376 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      | \
 377                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
 378                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 379
 380 /*-----------------------------------------------------------------------
 381  * Internal Definitions
 382  *-----------------------------------------------------------------------
 383  *
 384  */
 385
 386 /*
 387  * Boot Flags
 388  */
 389 #define BOOTFLAG_COLD   0x01             /* Normal Power-On: Boot from FLASH */
 390 #define BOOTFLAG_WARM   0x02             /* Software reboot                  */
 391
 392
 393 #endif  /* __CONFIG_H */