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Blackfin: unify default I2C settings for ADI boards
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1 /*
2 * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
3 * Scott McNutt <smcnutt@psyent.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*------------------------------------------------------------------------
28 * BOARD/CPU
29 *----------------------------------------------------------------------*/
30 #define CONFIG_EP1S10 1 /* EP1S10 board */
31 #define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
32
33 #define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
34 #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
35 #define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */
36
37 /*------------------------------------------------------------------------
38 * CACHE -- the following will support II/s and II/f. The II/s does not
39 * have dcache, so the cache instructions will behave as NOPs.
40 *----------------------------------------------------------------------*/
41 #define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
42 #define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
43 #define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
44 #define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
45
46 /*------------------------------------------------------------------------
47 * MEMORY BASE ADDRESSES
48 *----------------------------------------------------------------------*/
49 #define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
50 #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
51 #define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
52 #define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
53 #define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */
54 #define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */
55
56 /*------------------------------------------------------------------------
57 * MEMORY ORGANIZATION
58 * -Monitor at top.
59 * -The heap is placed below the monitor.
60 * -Global data is placed below the heap.
61 * -The stack is placed below global data (&grows down).
62 *----------------------------------------------------------------------*/
63 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */
64 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/
65 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
66
67 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
68 #define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
69 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
70 #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
71
72 /*------------------------------------------------------------------------
73 * FLASH (AM29LV065D)
74 *----------------------------------------------------------------------*/
75 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
76 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
77 #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
78 #define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
79
80 /*------------------------------------------------------------------------
81 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
82 * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
83 * of flash memory. This will keep the environment in user region
84 * of flash. NOTE: the monitor length must be multiple of sector size
85 * (which is common practice).
86 *----------------------------------------------------------------------*/
87 #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
88 #define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
89 #define CONFIG_ENV_OVERWRITE /* Serial change Ok */
90 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
91
92 /*------------------------------------------------------------------------
93 * CONSOLE
94 *----------------------------------------------------------------------*/
95 #define CONFIG_ALTERA_UART 1 /* Use altera uart */
96 #if defined(CONFIG_ALTERA_JTAG_UART)
97 #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
98 #else
99 #define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */
100 #endif
101
102 #define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
103 #define CONFIG_BAUDRATE 115200 /* Initial baudrate */
104 #define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
105
106 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
107
108 /*------------------------------------------------------------------------
109 * EPCS Device -- None for stratix.
110 *----------------------------------------------------------------------*/
111 #undef CONFIG_SYS_NIOS_EPCSBASE
112
113 /*------------------------------------------------------------------------
114 * DEBUG
115 *----------------------------------------------------------------------*/
116 #undef CONFIG_ROM_STUBS /* Stubs not in ROM */
117
118 /*------------------------------------------------------------------------
119 * TIMEBASE --
120 *
121 * The high res timer defaults to 1 msec. Since it includes the period
122 * registers, the interrupt frequency can be reduced using TMRCNT.
123 * If the default period is acceptable, TMRCNT can be left undefined.
124 * TMRMS represents the desired mecs per tick (msecs per interrupt).
125 *----------------------------------------------------------------------*/
126 #define CONFIG_SYS_HZ 1000 /* Always 1000 */
127 #define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
128 #define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
129 #define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
130 #define CONFIG_SYS_NIOS_TMRCNT \
131 (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
132
133 /*------------------------------------------------------------------------
134 * STATUS LED -- Provides a simple blinking led. For Nios2 each board
135 * must implement its own led routines -- since leds are board-specific.
136 *----------------------------------------------------------------------*/
137 #define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
138 #define CONFIG_STATUS_LED /* Enable status driver */
139
140 #define STATUS_LED_BIT 1 /* Bit-0 on PIO */
141 #define STATUS_LED_STATE 1 /* Blinking */
142 #define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */
143
144 /*------------------------------------------------------------------------
145 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
146 * and really doesn't need any additional clutter. So I choose the lazy
147 * way out to avoid changes there -- define the base address to ensure
148 * cache bypass so there's no need to monkey with inx/outx macros.
149 *----------------------------------------------------------------------*/
150 #define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
151 #define CONFIG_NET_MULTI
152 #define CONFIG_SMC91111 /* Using SMC91c111 */
153 #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
154 #define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
155
156 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
157 #define CONFIG_NETMASK 255.255.255.0
158 #define CONFIG_IPADDR 192.168.2.21
159 #define CONFIG_SERVERIP 192.168.2.16
160
161
162 /*
163 * BOOTP options
164 */
165 #define CONFIG_BOOTP_BOOTFILESIZE
166 #define CONFIG_BOOTP_BOOTPATH
167 #define CONFIG_BOOTP_GATEWAY
168 #define CONFIG_BOOTP_HOSTNAME
169
170
171 /*
172 * Command line configuration.
173 */
174 #define CONFIG_CMD_BDI
175 #define CONFIG_CMD_DHCP
176 #define CONFIG_CMD_ECHO
177 #define CONFIG_CMD_SAVEENV
178 #define CONFIG_CMD_FLASH
179 #define CONFIG_CMD_IMI
180 #define CONFIG_CMD_IRQ
181 #define CONFIG_CMD_LOADS
182 #define CONFIG_CMD_LOADB
183 #define CONFIG_CMD_MEMORY
184 #define CONFIG_CMD_MISC
185 #define CONFIG_CMD_NET
186 #define CONFIG_CMD_PING
187 #define CONFIG_CMD_RUN
188 #define CONFIG_CMD_SAVES
189
190
191 /*------------------------------------------------------------------------
192 * MISC
193 *----------------------------------------------------------------------*/
194 #define CONFIG_SYS_LONGHELP /* Provide extended help*/
195 #define CONFIG_SYS_PROMPT "==> " /* Command prompt */
196 #define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
197 #define CONFIG_SYS_MAXARGS 16 /* Max command args */
198 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
199 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
200 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
201 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
202 #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
203
204 #define CONFIG_SYS_HUSH_PARSER
205 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
206
207 #endif /* __CONFIG_H */