include/configs/EP88x.h

   1 /*
   2  * Copyright (C) 2005 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Support for Embedded Planet EP88x boards.
   6  * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #define CONFIG_MPC885
  30
  31 #define CONFIG_EP88X                            /* Embedded Planet EP88x board  */
  32
  33 #define CONFIG_BOARD_EARLY_INIT_F               /* Call board_early_init_f      */
  34
  35 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  36 #define CONFIG_ENV_OVERWRITE
  37
  38 #define CONFIG_8xx_CONS_SMC1    1               /* Console is on SMC1           */
  39 #define CONFIG_BAUDRATE         38400
  40
  41 #define CONFIG_ETHER_ON_FEC1                    /* Enable Ethernet on FEC1      */
  42 #define CONFIG_ETHER_ON_FEC2                    /* Enable Ethernet on FEC2      */
  43 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
  44 #define CFG_DISCOVER_PHY
  45 #define FEC_ENET
  46 #endif /* CONFIG_FEC_ENET */
  47
  48 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK */
  49 #define CONFIG_8xx_CPUCLK_DEFAULT       100000000
  50 #define CFG_8xx_CPUCLK_MIN              40000000
  51 #define CFG_8xx_CPUCLK_MAX              133000000
  52
  53 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL  \
  54                                 | CFG_CMD_DHCP   \
  55                                 | CFG_CMD_IMMAP  \
  56                                 | CFG_CMD_MII    \
  57                                 | CFG_CMD_PING   \
  58                                 )
  59
  60 /* This must be included AFTER the definition of CONFIG_COMMANDS */
  61 #include <cmd_confdefs.h>
  62
  63 #define CONFIG_BOOTDELAY        5               /* Autoboot after 5 seconds     */
  64 #define CONFIG_BOOTCOMMAND      "bootm fe060000"        /* Autoboot command     */
  65 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
  66
  67 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
  68 #undef  CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
  69
  70 /*-----------------------------------------------------------------------
  71  * Miscellaneous configurable options
  72  */
  73 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
  74 #define CFG_HUSH_PARSER
  75 #define CFG_PROMPT_HUSH_PS2     "> "
  76 #define CFG_LONGHELP                            /* #undef to save memory        */
  77 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  78 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
  79 #define CFG_MAXARGS             16              /* Max number of command args   */
  80 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  81
  82 #define CFG_LOAD_ADDR           0x400000        /* Default load address         */
  83
  84 #define CFG_HZ                  1000            /* Decrementer freq: 1 ms ticks */
  85
  86 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  87
  88 /*-----------------------------------------------------------------------
  89  * RAM configuration (note that CFG_SDRAM_BASE must be zero)
  90  */
  91 #define CFG_SDRAM_BASE          0x00000000
  92 #define CFG_SDRAM_MAX_SIZE      0x08000000      /* Up to 128 Mbyte              */
  93
  94 #define CFG_MAMR                0x00805000
  95
  96 /*
  97  * 4096 Up to 4096 SDRAM rows
  98  * 1000 factor s -> ms
  99  * 32   PTP (pre-divider from MPTPR)
 100  * 4    Number of refresh cycles per period
 101  * 64   Refresh cycle in ms per number of rows
 102  */
 103 #define CFG_PTA_PER_CLK         ((4096 * 32 * 1000) / (4 * 64))
 104
 105 #define CFG_MEMTEST_START       0x00100000      /* memtest works on             */
 106 #define CFG_MEMTEST_END         0x00500000      /* 1 ... 5 MB in SDRAM          */
 107
 108 #define CFG_RESET_ADDRESS       0x09900000
 109
 110 /*-----------------------------------------------------------------------
 111  * For booting Linux, the board info and command line data
 112  * have to be in the first 8 MB of memory, since this is
 113  * the maximum mapped by the Linux kernel during initialization.
 114  */
 115 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 116
 117 #define CFG_MONITOR_BASE        TEXT_BASE
 118 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 KB for Monitor   */
 119 #ifdef CONFIG_BZIP2
 120 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve ~4 MB for malloc()   */
 121 #else
 122 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 123 #endif /* CONFIG_BZIP2 */
 124
 125 /*-----------------------------------------------------------------------
 126  * Flash organisation
 127  */
 128 #define CFG_FLASH_BASE          0xFC000000
 129 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 130 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 131 #define CFG_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
 132 #define CFG_MAX_FLASH_SECT      512             /* Max num of sects on one chip */
 133
 134 /* Environment is in flash */
 135 #define CFG_ENV_IS_IN_FLASH
 136 #define CFG_ENV_SECT_SIZE       0x20000         /* We use one complete sector   */
 137 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 138
 139 #define CFG_OR0_PRELIM          0xFC000160
 140 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
 141
 142 #define CFG_DIRECT_FLASH_TFTP
 143
 144 /*-----------------------------------------------------------------------
 145  * BCSR
 146  */
 147 #define CFG_OR3_PRELIM          0xFF0005B0
 148 #define CFG_BR3_PRELIM          (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
 149
 150 #define CFG_BCSR                0xFA400000
 151
 152 /*-----------------------------------------------------------------------
 153  * Internal Memory Map Register
 154  */
 155 #define CFG_IMMR                0xF0000000
 156
 157 /*-----------------------------------------------------------------------
 158  * Definitions for initial stack pointer and data area (in DPRAM)
 159  */
 160 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 161 #define CFG_INIT_RAM_END        0x2F00          /* End of used area in DPRAM    */
 162 #define CFG_GBL_DATA_SIZE       128  /* Size in bytes reserved for initial data */
 163 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 164 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 165
 166 /*-----------------------------------------------------------------------
 167  * Configuration registers
 168  */
 169 #ifdef CONFIG_WATCHDOG
 170 #define CFG_SYPCR               (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 171                                  SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
 172                                  SYPCR_SWP)
 173 #else
 174 #define CFG_SYPCR               (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 175                                  SYPCR_SWF  | SYPCR_SWP)
 176 #endif /* CONFIG_WATCHDOG */
 177
 178 #define CFG_SIUMCR              (SIUMCR_MLRC01 | SIUMCR_DBGC11)
 179
 180 /* TBSCR - Time Base Status and Control Register */
 181 #define CFG_TBSCR               (TBSCR_TBF | TBSCR_TBE)
 182
 183 /* PISCR - Periodic Interrupt Status and Control */
 184 #define CFG_PISCR               PISCR_PS
 185
 186 /* SCCR - System Clock and reset Control Register */
 187 #define SCCR_MASK               SCCR_EBDF11
 188 #define CFG_SCCR                SCCR_RTSEL
 189
 190 #define CFG_DER                 0
 191
 192 /*-----------------------------------------------------------------------
 193  * Cache Configuration
 194  */
 195 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx chips                 */
 196
 197 /*-----------------------------------------------------------------------
 198  * Internal Definitions
 199  *
 200  * Boot Flags
 201  */
 202 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from flash     */
 203 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 204
 205 #endif /* __CONFIG_H */