include/configs/ERIC.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_ERIC             1       /* ...on a ERIC board   */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* run board_early_init_f() */
  41
  42 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  43
  44 #if 1
  45 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars       */
  46 #endif
  47 #if 0
  48 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
  49 #endif
  50 #if 0
  51 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use I2C RTC X1240 for environment vars */
  52 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
  53 #define CONFIG_ENV_SIZE         0x800   /* 2048 bytes may be used for env vars */
  54 #endif                                  /* total size of a X1240 is 2048 bytes */
  55
  56 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
  57 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
  58 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
  59 #define CONFIG_SYS_I2C_SLAVE            0x7F
  60
  61 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57    /* X1240 has two I2C slave addresses, one for EEPROM */
  62 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* address length for the eeprom */
  63 #define CONFIG_I2C_RTC          1       /* we have a Xicor X1240 RTC */
  64 #define CONFIG_SYS_I2C_RTC_ADDR 0x6F    /*                                and one for RTC */
  65
  66 #ifdef CONFIG_ENV_IS_IN_FLASH
  67 #undef CONFIG_ENV_IS_IN_NVRAM
  68 #undef CONFIG_ENV_IS_IN_EEPROM
  69 #else
  70 #ifdef CONFIG_ENV_IS_IN_NVRAM
  71 #undef CONFIG_ENV_IS_IN_FLASH
  72 #undef CONFIG_ENV_IS_IN_EEPROM
  73 #else
  74 #ifdef CONFIG_ENV_IS_IN_EEPROM
  75 #undef CONFIG_ENV_IS_IN_NVRAM
  76 #undef CONFIG_ENV_IS_IN_FLASH
  77 #endif
  78 #endif
  79 #endif
  80
  81 #define CONFIG_BAUDRATE         115200
  82 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  83
  84 #if 1
  85 #define CONFIG_BOOTCOMMAND      "bootm ffc00000" /* autoboot command    */
  86 #else
  87 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  88 #endif
  89
  90 #define CONFIG_BOOTARGS         "console=ttyS0,115200 root=/dev/nfs "   \
  91                                 "nfsroot=192.168.1.2:/eric_root_devel " \
  92                                 "ip=192.168.1.22:192.168.1.2"
  93
  94 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  95 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  96
  97 #define CONFIG_PPC4xx_EMAC
  98 #define CONFIG_MII              1       /* MII PHY management           */
  99 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 100 #define CONFIG_NET_MULTI
 101
 102
 103 /*
 104  * BOOTP options
 105  */
 106 #define CONFIG_BOOTP_BOOTFILESIZE
 107 #define CONFIG_BOOTP_BOOTPATH
 108 #define CONFIG_BOOTP_GATEWAY
 109 #define CONFIG_BOOTP_HOSTNAME
 110
 111
 112 /*
 113  * Command line configuration.
 114  */
 115 #include <config_cmd_default.h>
 116
 117 #define CONFIG_CMD_PCI
 118 #define CONFIG_CMD_IRQ
 119 #define CONFIG_CMD_SAVEENV
 120 #define CONFIG_CMD_FLASH
 121
 122
 123 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 124
 125 /*
 126  * Miscellaneous configurable options
 127  */
 128 #undef  CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 129 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 130 #if defined(CONFIG_CMD_KGDB)
 131 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 132 #else
 133 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 134 #endif
 135 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 136 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 137 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 138
 139 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 140 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 141
 142 #define  CONFIG_SYS_EXT_SERIAL_CLOCK     14318180
 143
 144 /* The following table includes the supported baudrates */
 145 #define CONFIG_SYS_BAUDRATE_TABLE       \
 146         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 147          57600, 115200, 230400, 460800, 921600 }
 148
 149 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 150 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 151
 152 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 153
 154 /*-----------------------------------------------------------------------
 155  * PCI stuff
 156  *-----------------------------------------------------------------------
 157  */
 158 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 159 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 160 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 161
 162 #define CONFIG_PCI                      /* include pci support          */
 163 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 164 #undef  CONFIG_PCI_PNP                  /* no pci plug-and-play         */
 165                                         /* resource configuration       */
 166
 167 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743   /* PCI Vendor ID: Peppercon AG  */
 168 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405   /* PCI Device ID: 405GP         */
 169 #define CONFIG_SYS_PCI_PTM1LA   0xFFFC0000      /* point to flash               */
 170 #define CONFIG_SYS_PCI_PTM1MS   0xFFFFF001      /* 4kB, enable hard-wired to 1  */
 171 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 172 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 173 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 174 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 175
 176 /*-----------------------------------------------------------------------
 177  * External peripheral base address
 178  *-----------------------------------------------------------------------
 179  */
 180 /*      Bank 0 - Flash/SRAM            0xFF000000 16MB  16 Bit */
 181 /*      Bank 1 - NVRAM/RTC             0xF0000000  1MB   8 Bit */
 182 /*      Bank 2 - A/D converter         0xF0100000  1MB   8 Bit */
 183 /*      Bank 3 - Ethernet PHY Reset    0xF0200000  1MB   8 Bit */
 184 /*      Bank 4 - PC-MIP PRSNT1#        0xF0300000  1MB   8 Bit */
 185 /*      Bank 5 - PC-MIP PRSNT2#        0xF0400000  1MB   8 Bit */
 186 /*      Bank 6 - CPU LED0              0xF0500000  1MB   8 Bit */
 187 /*      Bank 7 - CPU LED1              0xF0600000  1MB   8 Bit */
 188
 189 /* ----------------------------------------------------------------------- */
 190 /*  Memory Bank 0 (Flash) initialization */
 191 /* ----------------------------------------------------------------------- */
 192 #define CS0_AP  0x9B015480
 193 #define CS0_CR  0xFF87A000 /*  BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
 194 /* ----------------------------------------------------------------------- */
 195 /*  Memory Bank 1 (NVRAM/RTC) initialization */
 196 /* ----------------------------------------------------------------------- */
 197 #define CS1_AP  0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 198 #define CS1_CR  0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 199  /* ----------------------------------------------------------------------- */
 200  /*  Memory Bank 2 (A/D converter) initialization */
 201  /* ----------------------------------------------------------------------- */
 202 #define CS2_AP  0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 203 #define CS2_CR  0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 204 /* ----------------------------------------------------------------------- */
 205 /*  Memory Bank 3 (Ethernet PHY Reset) initialization */
 206 /* ----------------------------------------------------------------------- */
 207 #define CS3_AP  0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 208 #define CS3_CR  0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 209 /* ----------------------------------------------------------------------- */
 210 /*  Memory Bank 4 (PC-MIP PRSNT1#) initialization */
 211 /* ----------------------------------------------------------------------- */
 212 #define CS4_AP  0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 213 #define CS4_CR  0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 214 /* ----------------------------------------------------------------------- */
 215 /*  Memory Bank 5 (PC-MIP PRSNT2#) initialization */
 216 /* ----------------------------------------------------------------------- */
 217 #define CS5_AP  0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 218 #define CS5_CR  0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 219 /* ----------------------------------------------------------------------- */
 220 /*  Memory Bank 6 (CPU LED0) initialization */
 221 /* ----------------------------------------------------------------------- */
 222 #define CS6_AP  0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 223 #define CS6_CR  0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 224 /* ----------------------------------------------------------------------- */
 225 /*  Memory Bank 7 (CPU LED1) initialization */
 226 /* ----------------------------------------------------------------------- */
 227 #define CS7_AP  0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
 228 #define CS7_CR  0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
 229
 230 #define CONFIG_SYS_NVRAM_REG_BASE_ADDR   0xF0000000
 231 #define CONFIG_SYS_RTC_REG_BASE_ADDR     (0xF0000000 + 0x7F8)
 232 #define CONFIG_SYS_ADC_REG_BASE_ADDR     0xF0100000
 233 #define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
 234 #define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
 235 #define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
 236 #define CONFIG_SYS_LED0_REG_BASE_ADDR    0xF0500000
 237 #define CONFIG_SYS_LED1_REG_BASE_ADDR    0xF0600000
 238
 239
 240 /*  SDRAM CONFIG */
 241 #define CONFIG_SYS_SDRAM_MANUALLY    1
 242 #define CONFIG_SYS_SDRAM_SINGLE_BANK 1
 243
 244 #ifdef CONFIG_SYS_SDRAM_MANUALLY
 245 /*-----------------------------------------------------------------------
 246  * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
 247  *----------------------------------------------------------------------*/
 248 #define MB0CF   0x00062001 /*  32MB @ 0 */
 249 /*-----------------------------------------------------------------------
 250  * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
 251  *----------------------------------------------------------------------*/
 252 #ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
 253 #define MB1CF   0x0 /*  0MB @ 32MB */
 254 #else
 255 #define MB1CF   0x02062001 /*  32MB @ 32MB */
 256 #endif
 257 /*-----------------------------------------------------------------------
 258  * Set MB2CF for bank 2. off
 259  *----------------------------------------------------------------------*/
 260 #define MB2CF   0x0 /*  0MB */
 261 /*-----------------------------------------------------------------------
 262  * Set MB3CF for bank 3. off
 263  *----------------------------------------------------------------------*/
 264 #define MB3CF   0x0 /*  0MB */
 265
 266 #define SDTR_100    0x0086400D
 267 #define RTR_100     0x05F0
 268 #define SDTR_66     0x00854006  /* orig U-Boot-wallnut says 0x00854006 */
 269 #define RTR_66      0x03f8
 270
 271 #endif   /* CONFIG_SYS_SDRAM_MANUALLY */
 272
 273
 274 /*-----------------------------------------------------------------------
 275  * Start addresses for the final memory configuration
 276  * (Set up by the startup code)
 277  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 278  */
 279 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 280 #define CONFIG_SYS_SDRAM_SIZE           32
 281 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* 8 MByte Flash */
 282 #define CONFIG_SYS_MONITOR_BASE 0xFFFE0000      /* last 128kByte within Flash */
 283 /*#define CONFIG_SYS_MONITOR_LEN                (192 * 1024)*/  /* Reserve 196 kB for Monitor   */
 284 #define CONFIG_SYS_MONITOR_LEN          (128 * 1024)    /* Reserve 128 kB for Monitor   */
 285 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 286
 287 /*
 288  * For booting Linux, the board info and command line data
 289  * have to be in the first 8 MB of memory, since this is
 290  * the maximum mapped by the Linux kernel during initialization.
 291  */
 292 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 293 /*-----------------------------------------------------------------------
 294  * FLASH organization
 295  */
 296 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 297 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max number of sectors on one chip    */
 298 #define CONFIG_SYS_FLASH_16BIT          1       /* Rom 16 bit data bus                  */
 299
 300 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 301 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 302
 303 /* BEG ENVIRONNEMENT FLASH */
 304 #ifdef CONFIG_ENV_IS_IN_FLASH
 305 #define CONFIG_ENV_SECT_SIZE       (128*1024)
 306
 307 #if 0  /* force ENV to be NOT embedded */
 308 #define CONFIG_ENV_ADDR            0xfffa0000
 309 #else  /* force ENV to be embedded */
 310 #define CONFIG_ENV_SIZE         (2 * 1024) /* Total Size of Environment Sector 2k */
 311 #define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
 312 /* #define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE)*/
 313 #define CONFIG_ENV_OFFSET          (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 314 #endif
 315
 316 #endif
 317 /* END ENVIRONNEMENT FLASH */
 318 /*-----------------------------------------------------------------------
 319  * NVRAM organization
 320  */
 321 #define CONFIG_SYS_NVRAM_BASE_ADDR      CONFIG_SYS_NVRAM_REG_BASE_ADDR  /* NVRAM base address   */
 322 #define CONFIG_SYS_NVRAM_SIZE           0x7F8           /* NVRAM size 2kByte - 8 Byte for RTC */
 323
 324 #ifdef CONFIG_ENV_IS_IN_NVRAM
 325 #define CONFIG_ENV_SIZE         0x7F8           /* Size of Environment vars     */
 326 #define CONFIG_ENV_ADDR         \
 327         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)      /* Env  */
 328 #endif
 329
 330 /*
 331  * Init Memory Controller:
 332  *
 333  * BR0/1 and OR0/1 (FLASH)
 334  */
 335
 336 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0 8MB    */
 337 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 338
 339
 340 /* Configuration Port location */
 341 /*  #define CONFIG_PORT_ADDR    0xF0000500 */
 342
 343 /*-----------------------------------------------------------------------
 344  * Definitions for initial stack pointer and data area (in DPRAM)
 345  */
 346 #define CONFIG_SYS_INIT_RAM_ADDR        0x00df0000  /* inside of SDRAM                 */
 347 #define CONFIG_SYS_INIT_RAM_END 0x0f00  /* End of used area in RAM             */
 348 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 349 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 350 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 351
 352 /*-----------------------------------------------------------------------
 353  * Definitions for Serial Presence Detect EEPROM address
 354  * (to get SDRAM settings)
 355  */
 356 #define SPD_EEPROM_ADDRESS      0x50
 357
 358 /*
 359  * Internal Definitions
 360  *
 361  * Boot Flags
 362  */
 363 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 364 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 365
 366 #if defined(CONFIG_CMD_KGDB)
 367 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 368 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 369 #endif
 370 #endif  /* __CONFIG_H */