include/configs/ESTEEM192E.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  37 #define CONFIG_ESTEEM192E       1       /* ...on a EST ESTEEM192E       */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0x40000000
  40
  41 #define CONFIG_FLASH_16BIT      1       /* Rom 16 bit data bus          */
  42
  43 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  44 #undef  CONFIG_8xx_CONS_SMC2
  45 #undef  CONFIG_8xx_CONS_NONE
  46
  47 #define MPC8XX_FACT     10              /* Multiply by 10               */
  48 #define MPC8XX_XIN      4915200 /* 4.915200 MHz in      - ??? - XXX     */
  49 #define CONFIG_SYS_PLPRCR_MF    ((MPC8XX_FACT-1) << 20)
  50 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz       */
  51
  52 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_HZ       /* Force it - dont measure it */
  53
  54 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  55
  56 #define CONFIG_BAUDRATE         9600
  57 #if 0
  58 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  59 #else
  60 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  61 #endif
  62 #define CONFIG_BOOTCOMMAND      "bootm 40030000" /* autoboot command    */
  63
  64 #define CONFIG_BOOTARGS         "root=/dev/ram rw ramdisk=8192 "                        \
  65                                 "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
  66 /*
  67  * Miscellaneous configurable options
  68  */
  69
  70 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  71 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  72
  73 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  74
  75 /*
  76  * BOOTP options
  77  */
  78 #define CONFIG_BOOTP_SUBNETMASK
  79 #define CONFIG_BOOTP_GATEWAY
  80 #define CONFIG_BOOTP_HOSTNAME
  81 #define CONFIG_BOOTP_BOOTPATH
  82 #define CONFIG_BOOTP_BOOTFILESIZE
  83
  84
  85 /*
  86  * Command line configuration.
  87  */
  88 #include <config_cmd_default.h>
  89
  90
  91 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  92 #define CONFIG_SYS_PROMPT       "BOOT: "        /* Monitor Command Prompt       */
  93 #define CONFIG_SYS_CBSIZE       256                     /* Console I/O Buffer Size      */
  94 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  95 #define CONFIG_SYS_MAXARGS      8                       /* max number of command args   */
  96 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  97
  98 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  99 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 100
 101 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 102
 103 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 104
 105 /*
 106  * Low Level Configuration Settings
 107  * (address mappings, register initial values, etc.)
 108  * You should know what you are doing if you make changes here.
 109  */
 110 /*-----------------------------------------------------------------------
 111  * Internal Memory Mapped Register
 112  */
 113 #define CONFIG_SYS_IMMR         0xFF000000
 114
 115   /*-----------------------------------------------------------------------
 116  * Definitions for initial stack pointer and data area (in DPRAM)
 117  */
 118 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 119 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 120 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 121 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 122
 123
 124 /*-----------------------------------------------------------------------
 125  * Start addresses for the final memory configuration
 126  * (Set up by the startup code)
 127  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 128  */
 129 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 130 #define CONFIG_SYS_FLASH_BASE           0x40000000
 131 #ifdef  DEBUG
 132 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 133 #else
 134 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 135 #endif
 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 137 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 138
 139 /*
 140  * For booting Linux, the board info and command line data
 141  * have to be in the first 8 MB of memory, since this is
 142  * the maximum mapped by the Linux kernel during initialization.
 143  */
 144 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 145 /*-----------------------------------------------------------------------
 146  * FLASH organization
 147  */
 148 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 149 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip    */
 150
 151 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 152 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 153
 154 #define CONFIG_ENV_IS_IN_FLASH  1
 155 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 156 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 157 /*-----------------------------------------------------------------------
 158  * Cache Configuration
 159  */
 160 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 161
 162 /*-----------------------------------------------------------------------
 163  * SYPCR - System Protection Control                            11-9
 164  * SYPCR can only be written once after reset!
 165  *-----------------------------------------------------------------------
 166  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 167  */
 168 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 169
 170 /*-----------------------------------------------------------------------
 171  * SUMCR - SIU Module Configuration                             11-6
 172  *-----------------------------------------------------------------------
 173  * PCMCIA config., multi-function pin tri-state
 174  */
 175 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
 176
 177 /*-----------------------------------------------------------------------
 178  * TBSCR - Time Base Status and Control                         11-26
 179  *-----------------------------------------------------------------------
 180  * Clear Reference Interrupt Status, Timebase freezing enabled
 181  */
 182 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 183
 184 /* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
 185
 186
 187 /*-----------------------------------------------------------------------
 188  * PISCR - Periodic Interrupt Status and Control                11-31
 189  *-----------------------------------------------------------------------
 190  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 191  */
 192 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 193
 194 /*-----------------------------------------------------------------------
 195  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 196  *-----------------------------------------------------------------------
 197  * Reset PLL lock status sticky bit, timer expired status bit and timer
 198  * interrupt status bit - leave PLL multiplication factor unchanged !
 199  */
 200 #define CONFIG_SYS_PLPRCR       (CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 201
 202 /*-----------------------------------------------------------------------
 203  * SCCR - System Clock and reset Control Register               15-27
 204  *-----------------------------------------------------------------------
 205  * Set clock output, timebase and RTC source and divider,
 206  * power management and some other internal clocks
 207  */
 208 #define SCCR_MASK       SCCR_EBDF11
 209 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 210                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 211                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 212                          SCCR_DFALCD00)
 213
 214 /*-----------------------------------------------------------------------
 215  * PCMCIA stuff
 216  *-----------------------------------------------------------------------
 217  *
 218  */
 219 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 220 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 221 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 222 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 223 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 224 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 225 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 226 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 227
 228 #define CONFIG_SYS_PCMCIA_INTERRUPT     SIU_LEVEL6
 229
 230 /*-----------------------------------------------------------------------
 231  *
 232  *-----------------------------------------------------------------------
 233  *
 234  */
 235 /*#define       CONFIG_SYS_DER  0x2002000F*/
 236 #define CONFIG_SYS_DER  0
 237 /*#define CONFIG_SYS_DER        0x02002000 */
 238
 239
 240 /*
 241  * Init Memory Controller:
 242  *
 243  * BR0/1 and OR0/1 (FLASH)
 244  */
 245
 246 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 247 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 248
 249 /* used to re-map FLASH both when starting from SRAM or FLASH:
 250  * restrict access enough to keep SRAM working (if any)
 251  * but not too much to meddle with FLASH accesses
 252  */
 253 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 254 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 255
 256 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 257 #define CONFIG_SYS_OR_TIMING_FLASH      0x00000160
 258                                 /*(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 259                                  OR_SCY_5_CLK | OR_EHTR) */
 260
 261 #define CONFIG_SYS_OR0_REMAP    0x80000160     /*(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)*/
 262 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 263 #define CONFIG_SYS_BR0_PRELIM   ( FLASH_BASE0_PRELIM | 0x00000801 )
 264
 265 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 266 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 267 #define CONFIG_SYS_BR1_PRELIM   ( FLASH_BASE1_PRELIM | 0x00000801 )
 268
 269 /*
 270  * BR2/3 and OR2/3 (SDRAM)
 271  *
 272  */
 273 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 274 #define SDRAM_BASE3_PRELIM      0x04000000      /* SDRAM bank #1        */
 275 #define SDRAM_MAX_SIZE          0x02000000      /* max 32 MB per bank   */
 276
 277 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 278 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 279
 280 #define CONFIG_SYS_OR2_PRELIM   0xFC000E00
 281 #define CONFIG_SYS_BR2_PRELIM   (SDRAM_BASE2_PRELIM | 0x00000081)
 282
 283 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 284 #define CONFIG_SYS_BR3_PRELIM   (SDRAM_BASE3_PRELIM | 0x00000081)
 285
 286
 287 /*
 288  * Memory Periodic Timer Prescaler
 289  */
 290
 291 /* periodic timer for refresh */
 292 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz       */
 293
 294 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 295 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 296 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 297
 298 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 299 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 300 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 301
 302 /*
 303  * MAMR settings for SDRAM
 304  */
 305
 306 /* 8 column SDRAM */
 307 #define CONFIG_SYS_MAMR_8COL    0x18803112
 308 #define CONFIG_SYS_MAMR_9COL    0x18803112      /* same as 8 column because its just easier to port with*/
 309
 310 #endif  /* __CONFIG_H */