include/configs/FADS850SAR.h

   1  /*
   2   * A collection of structures, addresses, and values associated with
   3   * the Motorola 860T FADS board.  Copied from the MBX stuff.
   4   * Magnus Damm added defines for 8xxrom and extended bd_info.
   5   * Helmut Buchsbaum added bitvalues for BCSRx
   6   *
   7   * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
   8   */
   9
  10 /*
  11  * 1999-nov-26: The FADS is using the following physical memorymap:
  12  *
  13  * ff020000 -> ff02ffff : pcmcia
  14  * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
  15  * ff000000 -> ff00ffff : IMAP       internal in the cpu
  16  * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
  17  * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
  18  */
  19
  20 /* ------------------------------------------------------------------------- */
  21
  22 /*
  23  * board/config.h - configuration options, board specific
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  * (easy to change)
  32  */
  33 #define CONFIG_MPC850           1
  34 #define CONFIG_MPC850SAR        1
  35 #define CONFIG_FADS                     1
  36
  37 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  38
  39 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  40 #undef  CONFIG_8xx_CONS_SMC2
  41 #undef  CONFIG_8xx_CONS_NONE
  42 #define CONFIG_BAUDRATE         9600
  43
  44 #if 0
  45 #define MPC8XX_FACT     10                              /* Multiply by 10               */
  46 #define MPC8XX_XIN      50000000                /* 50 MHz in    */
  47 #else
  48 #define MPC8XX_FACT     12                              /* Multiply by 12 */
  49 #define MPC8XX_XIN      4000000                 /* 4 MHz in */
  50 #endif
  51 #define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
  52
  53 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  54
  55 #if 1
  56 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  57 #else
  58 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  59 #endif
  60
  61 #define CONFIG_BOOTCOMMAND      "bootm 02880000"        /* autoboot command */
  62 #define CONFIG_BOOTARGS         " "
  63
  64 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  65
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_BOOTFILESIZE
  71 #define CONFIG_BOOTP_BOOTPATH
  72 #define CONFIG_BOOTP_GATEWAY
  73 #define CONFIG_BOOTP_HOSTNAME
  74
  75
  76 /*
  77  * Command line configuration.
  78  */
  79 #include <config_cmd_default.h>
  80
  81
  82 /*
  83  * Miscellaneous configurable options
  84  */
  85 #undef  CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  86 #define CONFIG_SYS_PROMPT               ":>"            /* Monitor Command Prompt       */
  87 #if defined(CONFIG_CMD_KGDB)
  88 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  89 #else
  90 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  91 #endif
  92 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  93 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  94 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  95
  96 #define CONFIG_SYS_MEMTEST_START        0x00004000      /* memtest works on     */
  97 #define CONFIG_SYS_MEMTEST_END          0x00800000      /* 0 ... 8 MB in DRAM   */
  98
  99 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 100
 101 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 102
 103 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 104
 105 /*
 106  * Low Level Configuration Settings
 107  * (address mappings, register initial values, etc.)
 108  * You should know what you are doing if you make changes here.
 109  */
 110 /*-----------------------------------------------------------------------
 111  * Internal Memory Mapped Register
 112  */
 113 #define CONFIG_SYS_IMMR                 0xFF000000
 114 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
 115
 116 /*-----------------------------------------------------------------------
 117  * Definitions for initial stack pointer and data area (in DPRAM)
 118  */
 119 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 120 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 121 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 122 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 123
 124 /*-----------------------------------------------------------------------
 125  * Start addresses for the final memory configuration
 126  * (Set up by the startup code)
 127  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 128  * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
 129  */
 130 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 131 #define CONFIG_SYS_SDRAM_SIZE           (4<<20) /* standard FADS has 4M */
 132 #define CONFIG_SYS_FLASH_BASE           0x02800000
 133 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 134 #if 0
 135 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 128 kB for Monitor   */
 136 #else
 137 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 512 kB for Monitor   */
 138 #endif
 139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 140 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 128 kB for malloc()  */
 141
 142 /*
 143  * For booting Linux, the board info and command line data
 144  * have to be in the first 8 MB of memory, since this is
 145  * the maximum mapped by the Linux kernel during initialization.
 146  */
 147 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 148 /*-----------------------------------------------------------------------
 149  * FLASH organization
 150  */
 151 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 152 #define CONFIG_SYS_MAX_FLASH_SECT       8       /* max number of sectors on one chip    */
 153
 154 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 155 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 156
 157 #define CONFIG_ENV_IS_IN_FLASH  1
 158 #define CONFIG_ENV_OFFSET               0x00040000      /* Offset of Environment Sector */
 159 #define CONFIG_ENV_SIZE         0x40000 /* Total Size of Environment Sector     */
 160 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 161
 162 /*-----------------------------------------------------------------------
 163  * Cache Configuration
 164  */
 165 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 166 #if defined(CONFIG_CMD_KGDB)
 167 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 168 #endif
 169
 170 /*-----------------------------------------------------------------------
 171  * SYPCR - System Protection Control                                    11-9
 172  * SYPCR can only be written once after reset!
 173  *-----------------------------------------------------------------------
 174  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 175  */
 176 #if defined(CONFIG_WATCHDOG)
 177 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 178                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 179 #else
 180 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 181 #endif
 182
 183 /*-----------------------------------------------------------------------
 184  * SIUMCR - SIU Module Configuration                                            11-6
 185  *-----------------------------------------------------------------------
 186  * PCMCIA config., multi-function pin tri-state
 187  */
 188 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 189
 190 /*-----------------------------------------------------------------------
 191  * TBSCR - Time Base Status and Control                                 11-26
 192  *-----------------------------------------------------------------------
 193  * Clear Reference Interrupt Status, Timebase freezing enabled
 194  */
 195 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 196
 197 /*-----------------------------------------------------------------------
 198  * PISCR - Periodic Interrupt Status and Control                11-31
 199  *-----------------------------------------------------------------------
 200  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 201  */
 202 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 203
 204 /*-----------------------------------------------------------------------
 205  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 206  *-----------------------------------------------------------------------
 207  * Reset PLL lock status sticky bit, timer expired status bit and timer  *
 208  * interrupt status bit - leave PLL multiplication factor unchanged !
 209  */
 210 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << 20) | \
 211                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 212
 213 /*-----------------------------------------------------------------------
 214  * SCCR - System Clock and reset Control Register               15-27
 215  *-----------------------------------------------------------------------
 216  * Set clock output, timebase and RTC source and divider,
 217  * power management and some other internal clocks
 218  */
 219 #define SCCR_MASK       SCCR_EBDF11
 220 #define CONFIG_SYS_SCCR       (SCCR_TBS     | \
 221                                 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 222                                 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 223                                 SCCR_DFALCD00)
 224
 225  /*-----------------------------------------------------------------------
 226  *
 227  *-----------------------------------------------------------------------
 228  *
 229  */
 230 #define CONFIG_SYS_DER          0
 231
 232 /* Because of the way the 860 starts up and assigns CS0 the
 233 * entire address space, we have to set the memory controller
 234 * differently.  Normally, you write the option register
 235 * first, and then enable the chip select by writing the
 236 * base register.  For CS0, you must write the base register
 237 * first, followed by the option register.
 238 */
 239
 240 /*
 241  * Init Memory Controller:
 242  *
 243  * BR0/1 and OR0/1 (FLASH)
 244  */
 245 /* the other CS:s are determined by looking at parameters in BCSRx */
 246
 247
 248 #define BCSR_ADDR               ((uint) 0x02100000)
 249 #define BCSR_SIZE               ((uint)(64 * 1024))
 250
 251 #define FLASH_BASE0_PRELIM      0x02800000      /* FLASH bank #0        */
 252 #define FLASH_BASE1_PRELIM      0x00000000      /* FLASH bank #1        */
 253
 254 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 255 #define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000      /* OR addr mask */
 256
 257 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 258 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 259
 260 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 261 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
 262 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 263
 264 /* BCSRx - Board Control and Status Registers */
 265 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 266 #define CONFIG_SYS_OR1_PRELIM   0xffff8110                                                                      /* 64Kbyte address space */
 267 #define CONFIG_SYS_BR1_PRELIM   ((BCSR_ADDR) | BR_V )
 268
 269
 270 /*
 271  * Memory Periodic Timer Prescaler
 272  */
 273
 274 /* periodic timer for refresh */
 275 #define CONFIG_SYS_MAMR_PTA             97              /* start with divider for 100 MHz       */
 276
 277 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 278 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 279 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 280
 281 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 282 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 283 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 284
 285 /*
 286  * MAMR settings for SDRAM
 287  */
 288
 289 /* 8 column SDRAM */
 290 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 291                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 292                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 293 /* 9 column SDRAM */
 294 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 295                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 296                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 297
 298 #define CONFIG_SYS_MAMR         0x13a01114
 299
 300 /* values according to the manual */
 301
 302
 303 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
 304 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
 305
 306 #define BCSR0                   ((uint) (BCSR_ADDR + 00))
 307 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 308 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 309 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 310 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 311
 312 /* FADS bitvalues by Helmut Buchsbaum
 313  * see MPC8xxADS User's Manual for a proper description
 314  * of the following structures
 315  */
 316
 317 #define BCSR0_ERB       ((uint)0x80000000)
 318 #define BCSR0_IP        ((uint)0x40000000)
 319 #define BCSR0_BDIS      ((uint)0x10000000)
 320 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 321 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 322 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 323 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 324 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 325
 326 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 327 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 328 #define BCSR1_ETHEN              ((uint)0x20000000)
 329 #define BCSR1_IRDEN              ((uint)0x10000000)
 330 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 331 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 332 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 333 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 334 #define BCSR1_PCCEN              ((uint)0x00800000)
 335 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 336 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 337 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 338 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 339 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 340 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 341
 342 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 343 #define BCSR2_FLASH_PD_SHIFT     28
 344 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 345 #define BCSR2_DRAM_PD_SHIFT      23
 346 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 347 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 348
 349 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 350 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 351 #define BCSR3_BREVNR0            ((ushort)0x0080)
 352 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 353 #define BCSR3_BREVN1             ((ushort)0x0008)
 354 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 355
 356 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 357 #define BCSR4_TFPLDL             ((uint)0x40000000)
 358 #define BCSR4_TPSQEL             ((uint)0x20000000)
 359 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 360 #ifdef CONFIG_MPC823
 361 #define BCSR4_USB_EN             ((uint)0x08000000)
 362 #endif /* CONFIG_MPC823 */
 363 #ifdef CONFIG_MPC860SAR
 364 #define BCSR4_UTOPIA_EN          ((uint)0x08000000)
 365 #endif /* CONFIG_MPC860SAR */
 366 #ifdef CONFIG_MPC860T
 367 #define BCSR4_FETH_EN            ((uint)0x08000000)
 368 #endif /* CONFIG_MPC860T */
 369 #ifdef CONFIG_MPC823
 370 #define BCSR4_USB_SPEED          ((uint)0x04000000)
 371 #endif /* CONFIG_MPC823 */
 372 #ifdef CONFIG_MPC860T
 373 #define BCSR4_FETHCFG0           ((uint)0x04000000)
 374 #endif /* CONFIG_MPC860T */
 375 #ifdef CONFIG_MPC823
 376 #define BCSR4_VCCO               ((uint)0x02000000)
 377 #endif /* CONFIG_MPC823 */
 378 #ifdef CONFIG_MPC860T
 379 #define BCSR4_FETHFDE            ((uint)0x02000000)
 380 #endif /* CONFIG_MPC860T */
 381 #ifdef CONFIG_MPC823
 382 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
 383 #endif /* CONFIG_MPC823 */
 384 #ifdef CONFIG_MPC823
 385 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
 386 #endif /* CONFIG_MPC823 */
 387 #ifdef CONFIG_MPC860T
 388 #define BCSR4_FETHCFG1           ((uint)0x00400000)
 389 #endif /* CONFIG_MPC860T */
 390 #ifdef CONFIG_MPC823
 391 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
 392 #endif /* CONFIG_MPC823 */
 393 #ifdef CONFIG_MPC860T
 394 #define BCSR4_FETHRST            ((uint)0x00200000)
 395 #endif /* CONFIG_MPC860T */
 396 #define BCSR4_MODEM_EN           ((uint)0x00100000)
 397 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 398
 399 #define CONFIG_DRAM_50MHZ               1
 400 #define CONFIG_SDRAM_50MHZ
 401
 402 /* We don't use the 8259.
 403 */
 404 #define NR_8259_INTS    0
 405
 406 #define CONFIG_DISK_SPINUP_TIME 1000000
 407
 408
 409 /* PCMCIA configuration */
 410
 411 #define PCMCIA_MAX_SLOTS    2
 412
 413 #ifdef CONFIG_MPC860
 414 #define PCMCIA_SLOT_A 1
 415 #endif
 416
 417 #define CONFIG_SYS_DAUGHTERBOARD
 418
 419 #endif  /* __CONFIG_H */