include/configs/FADS860T.h

   1 /*
   2   * A collection of structures, addresses, and values associated with
   3   * the Motorola 860T FADS board.  Copied from the MBX stuff.
   4   * Magnus Damm added defines for 8xxrom and extended bd_info.
   5   * Helmut Buchsbaum added bitvalues for BCSRx
   6   *
   7   * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
   8   */
   9
  10 /*
  11  * 1999-nov-26: The FADS is using the following physical memorymap:
  12  *
  13  * ff020000 -> ff02ffff : pcmcia
  14  * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
  15  * ff000000 -> ff00ffff : IMAP       internal in the cpu
  16  * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
  17  * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
  18  */
  19
  20 /* ------------------------------------------------------------------------- */
  21
  22 /*
  23  * board/config.h - configuration options, board specific
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  * (easy to change)
  32  */
  33 #include <mpc8xx_irq.h>
  34
  35 /* board type */
  36 #define CONFIG_FADS             1       /* old/new FADS + new ADS */
  37
  38 /* processor type */
  39 #define CONFIG_MPC860T          1       /* 860T */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         38400
  45 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  46
  47 #if 0 /* old FADS */
  48 # define CFG_8XX_FACT           12              /* Multiply by 12 */
  49 # define CFG_8XX_XIN            4000000         /* 4 MHz in     */
  50 #else /* new FADS */
  51 # define CFG_8XX_FACT           10              /* Multiply by 10 */
  52 # define CFG_8XX_XIN            5000000         /* 5 MHz in     */
  53 #endif
  54
  55 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
  56
  57 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
  58 /* in general, we always know this for FADS+new ADS anyway */
  59 #define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ
  60
  61 /* most vanilla kernels do not like this, set to 0 if in doubt */
  62 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  63
  64 #if 1
  65 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  66 #else
  67 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  68 #endif
  69
  70 #undef  CONFIG_BOOTARGS
  71 #define CONFIG_BOOTCOMMAND                          \
  72     "bootp; "                               \
  73     "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  74     "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  75     "bootm"
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 /* ATA / IDE and partition support */
  80 #define CONFIG_MAC_PARTITION    1
  81 #define CONFIG_DOS_PARTITION    1
  82 #define CONFIG_ISO_PARTITION    1
  83 #undef  CONFIG_ATAPI
  84 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
  85 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
  86 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
  87 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
  88
  89 /* choose SCC1 ethernet (10BASET on motherboard)
  90  * or FEC ethernet (10/100 on daughterboard)
  91  */
  92 #if 0
  93 #define CONFIG_SCC1_ENET        1       /* use SCC1 ethernet */
  94 #undef  CONFIG_FEC_ENET                 /* disable FEC ethernet  */
  95 #else   /* all 86x cores have FECs, if in doubt, use it */
  96 #undef  CONFIG_SCC1_ENET                /* disable SCC1 ethernet */
  97 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
  98 #define CFG_DISCOVER_PHY
  99 #endif
 100 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 101 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 102 #endif
 103
 104 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 105 #include <cmd_confdefs.h>
 106
 107 /*
 108  * Miscellaneous configurable options
 109  */
 110 #undef  CFG_LONGHELP                    /* undef to save memory         */
 111 #define CFG_PROMPT              "=>"    /* Monitor Command Prompt       */
 112 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 113 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 114 #else
 115 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 116 #endif
 117 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 118 #define CFG_MAXARGS     16              /* max number of command args   */
 119 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 120
 121 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 122 #if (CFG_SDRAM_SIZE)
 123 #define CFG_MEMTEST_END         CFG_SDRAM_SIZE  /* 1 ... SDRAM_SIZE     */
 124 #else
 125 #define CFG_MEMTEST_END         0x0400000       /* 1 ... 4 MB in DRAM   */
 126 #endif
 127
 128 #define CFG_LOAD_ADDR           0x00100000
 129
 130 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 131
 132 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 133
 134 /*
 135  * Low Level Configuration Settings
 136  * (address mappings, register initial values, etc.)
 137  * You should know what you are doing if you make changes here.
 138  */
 139 /*----------------------------------------------------------------------
 140  * Internal Memory Mapped Register
 141  */
 142 #define CFG_IMMR                        0xFF000000
 143 #define CFG_IMMR_SIZE           ((uint)(64 * 1024))
 144
 145 /*-----------------------------------------------------------------------
 146  * Definitions for initial stack pointer and data area (in DPRAM)
 147  */
 148 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 149 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 150 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 151 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 152 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 153
 154 /*-----------------------------------------------------------------------
 155  * Start addresses for the final memory configuration
 156  * (Set up by the startup code)
 157  * Please note that CFG_SDRAM_BASE _must_ start at 0
 158  */
 159 #define CFG_SDRAM_BASE          0x00000000
 160 #ifdef CONFIG_FADS
 161 # define        CFG_SDRAM_SIZE  0x00400000      /* 4 meg */
 162 #else   /* !CONFIG_FADS */ /* old ADS */
 163 # define        CFG_SDRAM_SIZE  0x00000000      /* NO SDRAM */
 164 #endif
 165
 166 #define CFG_FLASH_BASE          0x02800000
 167
 168 #define CFG_FLASH_SIZE          ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 169
 170 #define CFG_MONITOR_LEN         (272 << 10)     /* Reserve 272 kB for Monitor   */
 171 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 172 #define CFG_MALLOC_LEN          (384 << 10)     /* Reserve 384 kB for malloc()  */
 173
 174 /*
 175  * For booting Linux, the board info and command line data
 176  * have to be in the first 8 MB of memory, since this is
 177  * the maximum mapped by the Linux kernel during initialization.
 178  */
 179 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 180 /*-----------------------------------------------------------------------
 181  * FLASH organization
 182  */
 183 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 184 #define CFG_MAX_FLASH_SECT      16      /* max number of sectors on one chip    */
 185
 186 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 187 #define CFG_FLASH_WRITE_TOUT    500             /* Timeout for Flash Write (in ms)      */
 188
 189 #define CFG_ENV_IS_IN_FLASH     1
 190 #define CFG_ENV_OFFSET          0x00040000
 191 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 192
 193 #define CFG_ENV_SECT_SIZE       0x40000 /* see README - env sector total size   */
 194
 195 /*-----------------------------------------------------------------------
 196  * Cache Configuration
 197  */
 198 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 199 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 200 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 201 #endif
 202
 203 /*-----------------------------------------------------------------------
 204  * SYPCR - System Protection Control                                    11-9
 205  * SYPCR can only be written once after reset!
 206  *-----------------------------------------------------------------------
 207  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 208  */
 209 #if defined(CONFIG_WATCHDOG)
 210 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 211                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 212 #else
 213 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 214 #endif
 215
 216 /*-----------------------------------------------------------------------
 217  * SIUMCR - SIU Module Configuration                                    11-6
 218  *-----------------------------------------------------------------------
 219  * PCMCIA config., multi-function pin tri-state
 220  */
 221 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 222
 223 /*-----------------------------------------------------------------------
 224  * TBSCR - Time Base Status and Control                                 11-26
 225  *-----------------------------------------------------------------------
 226  * Clear Reference Interrupt Status, Timebase freezing enabled
 227  */
 228 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 229
 230 /*-----------------------------------------------------------------------
 231  * PISCR - Periodic Interrupt Status and Control                11-31
 232  *-----------------------------------------------------------------------
 233  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 234  */
 235 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 236
 237 /*-----------------------------------------------------------------------
 238  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 239  *-----------------------------------------------------------------------
 240  * set the PLL, the low-power modes and the reset control (15-29)
 241  */
 242 #define CFG_PLPRCR      (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) |        \
 243                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 244
 245 /*-----------------------------------------------------------------------
 246  * SCCR - System Clock and reset Control Register               15-27
 247  *-----------------------------------------------------------------------
 248  * Set clock output, timebase and RTC source and divider,
 249  * power management and some other internal clocks
 250  */
 251 #define SCCR_MASK       SCCR_EBDF11
 252 #define CFG_SCCR        (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 253
 254  /*-----------------------------------------------------------------------
 255  *
 256  *-----------------------------------------------------------------------
 257  *
 258  */
 259 #define CFG_DER          0
 260
 261 /* Because of the way the 860 starts up and assigns CS0 the
 262 * entire address space, we have to set the memory controller
 263 * differently.  Normally, you write the option register
 264 * first, and then enable the chip select by writing the
 265 * base register.  For CS0, you must write the base register
 266 * first, followed by the option register.
 267 */
 268
 269 /*
 270  * Init Memory Controller:
 271  *
 272  * BR0/1 and OR0/1 (FLASH)
 273  */
 274 /* the other CS:s are determined by looking at parameters in BCSRx */
 275
 276 #define BCSR_ADDR               ((uint) 0xFF010000)
 277 #define BCSR_SIZE               ((uint)(64 * 1024))
 278
 279 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 280 #define CFG_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
 281
 282 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 283 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 284
 285 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 286
 287 #ifdef USE_REAL_FLASH_VALUES
 288 /*
 289  * These values fit our FADS860T ...
 290  * The "default" behaviour with 1Mbyte initial doesn't work for us!
 291  */
 292 #define CFG_OR0_PRELIM  0x0FFC00D34 /* Real values for the board */
 293 #define CFG_BR0_PRELIM  0x02800001  /* Real values for the board */
 294 #else
 295 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
 296 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
 297 #endif
 298
 299 /* BCSRx - Board Control and Status Registers */
 300 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 301 #define CFG_OR1_PRELIM  0xffff8110              /* 64Kbyte address space */
 302 #define CFG_BR1_PRELIM  ((BCSR_ADDR) | BR_V )
 303
 304 /*
 305  * Internal Definitions
 306  *
 307  * Boot Flags
 308  */
 309 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 310 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 311
 312
 313 /* values according to the manual */
 314
 315
 316 #define PCMCIA_MEM_ADDR         ((uint)0xff020000)
 317 #define PCMCIA_MEM_SIZE         ((uint)(64 * 1024))
 318
 319 #define BCSR0                   ((uint) (BCSR_ADDR + 00))
 320 #define BCSR1                   ((uint) (BCSR_ADDR + 0x04))
 321 #define BCSR2                   ((uint) (BCSR_ADDR + 0x08))
 322 #define BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
 323 #define BCSR4                   ((uint) (BCSR_ADDR + 0x10))
 324
 325 /* FADS bitvalues by Helmut Buchsbaum
 326  * see MPC8xxADS User's Manual for a proper description
 327  * of the following structures
 328  */
 329
 330 #define BCSR0_ERB       ((uint)0x80000000)
 331 #define BCSR0_IP        ((uint)0x40000000)
 332 #define BCSR0_BDIS      ((uint)0x10000000)
 333 #define BCSR0_BPS_MASK  ((uint)0x0C000000)
 334 #define BCSR0_ISB_MASK  ((uint)0x01800000)
 335 #define BCSR0_DBGC_MASK ((uint)0x00600000)
 336 #define BCSR0_DBPC_MASK ((uint)0x00180000)
 337 #define BCSR0_EBDF_MASK ((uint)0x00060000)
 338
 339 #define BCSR1_FLASH_EN           ((uint)0x80000000)
 340 #define BCSR1_DRAM_EN            ((uint)0x40000000)
 341 #define BCSR1_ETHEN              ((uint)0x20000000)
 342 #define BCSR1_IRDEN              ((uint)0x10000000)
 343 #define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
 344 #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
 345 #define BCSR1_BCSR_EN            ((uint)0x02000000)
 346 #define BCSR1_RS232EN_1          ((uint)0x01000000)
 347 #define BCSR1_PCCEN              ((uint)0x00800000)
 348 #define BCSR1_PCCVCC0            ((uint)0x00400000)
 349 #define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
 350 #define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
 351 #define BCSR1_RS232EN_2          ((uint)0x00040000)
 352 #define BCSR1_SDRAM_EN           ((uint)0x00020000)
 353 #define BCSR1_PCCVCC1            ((uint)0x00010000)
 354
 355 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
 356 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 357 #define BCSR2_DRAM_PD_SHIFT      (23)
 358 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
 359 #define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
 360
 361 #define BCSR3_DBID_MASK          ((ushort)0x3800)
 362 #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
 363 #define BCSR3_BREVNR0            ((ushort)0x0080)
 364 #define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
 365 #define BCSR3_BREVN1             ((ushort)0x0008)
 366 #define BCSR3_BREVN2_MASK        ((ushort)0x0003)
 367
 368 #define BCSR4_ETHLOOP            ((uint)0x80000000)
 369 #define BCSR4_TFPLDL             ((uint)0x40000000)
 370 #define BCSR4_TPSQEL             ((uint)0x20000000)
 371 #define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
 372 #ifdef CONFIG_MPC823
 373 #define BCSR4_USB_EN             ((uint)0x08000000)
 374 #endif /* CONFIG_MPC823 */
 375 #ifdef CONFIG_MPC860SAR
 376 #define BCSR4_UTOPIA_EN          ((uint)0x08000000)
 377 #endif /* CONFIG_MPC860SAR */
 378 #ifdef CONFIG_MPC860T
 379 #define BCSR4_FETH_EN            ((uint)0x08000000)
 380 #endif /* CONFIG_MPC860T */
 381 #ifdef CONFIG_MPC823
 382 #define BCSR4_USB_SPEED          ((uint)0x04000000)
 383 #endif /* CONFIG_MPC823 */
 384 #ifdef CONFIG_MPC860T
 385 #define BCSR4_FETHCFG0           ((uint)0x04000000)
 386 #endif /* CONFIG_MPC860T */
 387 #ifdef CONFIG_MPC823
 388 #define BCSR4_VCCO               ((uint)0x02000000)
 389 #endif /* CONFIG_MPC823 */
 390 #ifdef CONFIG_MPC860T
 391 #define BCSR4_FETHFDE            ((uint)0x02000000)
 392 #endif /* CONFIG_MPC860T */
 393 #ifdef CONFIG_MPC823
 394 #define BCSR4_VIDEO_ON           ((uint)0x00800000)
 395 #endif /* CONFIG_MPC823 */
 396 #ifdef CONFIG_MPC823
 397 #define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
 398 #endif /* CONFIG_MPC823 */
 399 #ifdef CONFIG_MPC860T
 400 #define BCSR4_FETHCFG1           ((uint)0x00400000)
 401 #endif /* CONFIG_MPC860T */
 402 #ifdef CONFIG_MPC823
 403 #define BCSR4_VIDEO_RST          ((uint)0x00200000)
 404 #endif /* CONFIG_MPC823 */
 405 #ifdef CONFIG_MPC860T
 406 #define BCSR4_FETHRST            ((uint)0x00200000)
 407 #endif /* CONFIG_MPC860T */
 408 #ifdef CONFIG_MPC823
 409 #define BCSR4_MODEM_EN           ((uint)0x00100000)
 410 #endif /* CONFIG_MPC823 */
 411 #ifdef CONFIG_MPC823
 412 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 413 #endif /* CONFIG_MPC823 */
 414 #ifdef CONFIG_MPC850
 415 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 416 #endif /* CONFIG_MPC850 */
 417
 418 #define CONFIG_DRAM_50MHZ               1
 419 #define CONFIG_SDRAM_50MHZ              1
 420
 421 #ifdef CONFIG_MPC860T
 422
 423 /* Interrupt level assignments.
 424 */
 425 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 426
 427 #endif /* CONFIG_MPC860T */
 428
 429 /* We don't use the 8259.
 430 */
 431 #define NR_8259_INTS    0
 432
 433 /* Machine type
 434 */
 435 #define _MACH_8xx (_MACH_fads)
 436
 437 #define CONFIG_DISK_SPINUP_TIME 1000000
 438
 439
 440 /* PCMCIA configuration */
 441
 442 #define PCMCIA_MAX_SLOTS    2
 443
 444 #ifdef CONFIG_MPC860
 445 #define PCMCIA_SLOT_A 1
 446 #endif
 447 /*#define CFG_PCMCIA_MEM_SIZE     ( 64 << 20) */
 448 #define CFG_PCMCIA_MEM_ADDR     (0x50000000)
 449 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 450 #define CFG_PCMCIA_DMA_ADDR     (0x54000000)
 451 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 452 #define CFG_PCMCIA_ATTRB_ADDR   (0x58000000)
 453 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 454 #define CFG_PCMCIA_IO_ADDR      (0x5C000000)
 455 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 456 /* we have 8 windows, we take everything up to 60000000 */
 457
 458 #define CFG_ATA_IDE0_OFFSET     0x0000
 459
 460 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 461
 462 /* Offset for data I/O                  */
 463 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 464 /* Offset for normal register accesses  */
 465 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 466 /* Offset for alternate registers       */
 467 #define CFG_ATA_ALT_OFFSET      0x0000
 468 /*#define CFG_ATA_ALT_OFFSET    0x0100 */
 469
 470
 471 #endif  /* __CONFIG_H */