include/configs/FLAGADM.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  37 #define CONFIG_FLAGADM          1       /* ...on a FLAGA DM     */
  38 #define CONFIG_8xx_GCLK_FREQ 48000000   /*48MHz*/
  39
  40 #undef  CONFIG_8xx_CONS_SMC1            /* Console is on SMC1           */
  41 #define CONFIG_8xx_CONS_SMC2    1
  42 #undef  CONFIG_8xx_CONS_NONE
  43
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  45 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds     */
  46
  47 #undef  CONFIG_CLOCKS_IN_MHZ
  48
  49 #if 0
  50 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=bootp"
  51 #define CONFIG_BOOTCOMMAND                                                      \
  52    "setenv bootargs root=/dev/ram ip=off panic=1;"     \
  53    "bootm 40040000 400e0000"
  54 #else
  55 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=bootp panic=1"
  56 #define CONFIG_BOOTCOMMAND      "bootp 0x400000; bootm 0x400000"
  57 #endif /* 0|1*/
  58
  59 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  60 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  61
  62 /*#define       CONFIG_WATCHDOG*/       /* watchdog enabled             */
  63 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  64
  65 /*
  66  * BOOTP options
  67  */
  68 #define CONFIG_BOOTP_SUBNETMASK
  69 #define CONFIG_BOOTP_GATEWAY
  70 #define CONFIG_BOOTP_HOSTNAME
  71 #define CONFIG_BOOTP_BOOTPATH
  72 #define CONFIG_BOOTP_BOOTFILESIZE
  73
  74
  75 /*
  76  * Command line configuration.
  77  */
  78
  79 #define CONFIG_CMD_BDI
  80 #define CONFIG_CMD_IMI
  81 #define CONFIG_CMD_CACHE
  82 #define CONFIG_CMD_MEMORY
  83 #define CONFIG_CMD_FLASH
  84 #define CONFIG_CMD_LOADB
  85 #define CONFIG_CMD_LOADS
  86 #define CONFIG_CMD_SAVEENV
  87 #define CONFIG_CMD_REGINFO
  88 #define CONFIG_CMD_IMMAP
  89 #define CONFIG_CMD_NET
  90
  91
  92 /*
  93  * Miscellaneous configurable options
  94  */
  95 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  96 #define CONFIG_SYS_PROMPT       "EEG> "         /* Monitor Command Prompt       */
  97 #if defined(CONFIG_CMD_KGDB)
  98 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  99 #else
 100 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 101 #endif
 102 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 103 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 104 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 105
 106 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 107 #define CONFIG_SYS_MEMTEST_END          0x0f00000       /* 1 ... 15 MB in DRAM  */
 108
 109 #define CONFIG_SYS_LOAD_ADDR            0x40040000      /* default load address */
 110
 111 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 112
 113 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 114
 115 /*
 116  * Low Level Configuration Settings
 117  * (address mappings, register initial values, etc.)
 118  * You should know what you are doing if you make changes here.
 119  */
 120 /*-----------------------------------------------------------------------
 121  * Internal Memory Mapped Register
 122  */
 123 #define CONFIG_SYS_IMMR         0xFF000000
 124
 125 /*-----------------------------------------------------------------------
 126  * Definitions for initial stack pointer and data area (in DPRAM)
 127  */
 128 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 129 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 130 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 131 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 132 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 133
 134 /*-----------------------------------------------------------------------
 135  * Start addresses for the final memory configuration
 136  * (Set up by the startup code)
 137  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 138  */
 139 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 140 #define CONFIG_SYS_FLASH_BASE           0x40000000
 141 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 143 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 144
 145 /*
 146  * For booting Linux, the board info and command line data
 147  * have to be in the first 8 MB of memory, since this is
 148  * the maximum mapped by the Linux kernel during initialization.
 149  */
 150 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 151
 152 /*-----------------------------------------------------------------------
 153  * FLASH organization
 154  */
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 156 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip    */
 157
 158 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000    /* Timeout for Flash Erase (in ms)      */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 160
 161 #define CONFIG_ENV_IS_IN_FLASH  1
 162 /* This is a litlebit wasteful, but one sector is 128kb and we have to
 163  * assigne a whole sector for the environment, so that we can safely
 164  * erase and write it without disturbing the boot sector
 165  */
 166 #define CONFIG_ENV_OFFSET               0x20000 /*   Offset   of Environment Sector     */
 167 #define CONFIG_ENV_SIZE         0x20000 /* Total Size of Environment Sector     */
 168
 169 /*-----------------------------------------------------------------------
 170  * Cache Configuration
 171  */
 172 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 173 #if defined(CONFIG_CMD_KGDB)
 174 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 175 #endif
 176 #define CONFIG_SYS_DELAYED_ICACHE       1       /* enable ICache not before
 177                                                  * running in RAM.
 178                                                  */
 179
 180 /*-----------------------------------------------------------------------
 181  * SYPCR - System Protection Control                            11-9
 182  * SYPCR can only be written once after reset!
 183  *-----------------------------------------------------------------------
 184  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 185  */
 186 #ifdef CONFIG_WATCHDOG
 187 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
 188 #else
 189 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 190 #endif
 191
 192 /*-----------------------------------------------------------------------
 193  * SIUMCR - SIU Module Configuration                            11-6
 194  *-----------------------------------------------------------------------
 195  * PCMCIA config., multi-function pin tri-state
 196  */
 197 #define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
 198                                                         SIUMCR_MLRC01 | SIUMCR_GB5E)
 199 #define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK)
 200
 201 /*-----------------------------------------------------------------------
 202  * TBSCR - Time Base Status and Control                         11-26
 203  *-----------------------------------------------------------------------
 204  * Clear Reference Interrupt Status, Timebase freezing enabled
 205  */
 206 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 207
 208 /*-----------------------------------------------------------------------
 209  * RTCSC - Real-Time Clock Status and Control Register          11-27
 210  *-----------------------------------------------------------------------
 211  */
 212 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 213
 214 /*-----------------------------------------------------------------------
 215  * PISCR - Periodic Interrupt Status and Control                11-31
 216  *-----------------------------------------------------------------------
 217  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 218  */
 219 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 220
 221 /*-----------------------------------------------------------------------
 222  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 223  *-----------------------------------------------------------------------
 224  * Reset PLL lock status sticky bit, timer expired status bit and timer
 225  * interrupt status bit miltiplier of 0x00b i.e. operation clock is
 226  * 4MHz * (0x00b+1) = 4MHz * 12 =  48MHz
 227  */
 228 #define CONFIG_SYS_PLPRCR       (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 229
 230 /*-----------------------------------------------------------------------
 231  * SCCR - System Clock and reset Control Register               15-27
 232  *-----------------------------------------------------------------------
 233  * Set clock output, timebase and RTC source and divider,
 234  * power management and some other internal clocks
 235  */
 236 #define SCCR_MASK       SCCR_EBDF11
 237 #define CONFIG_SYS_SCCR ( SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 238                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 239                          SCCR_DFALCD00)
 240
 241 #define CONFIG_SYS_DER 0
 242
 243 /*
 244  * In the Flaga DM we have:
 245  * Flash on BR0/OR0/CS0a at 0x40000000
 246  * Display on BR1/OR1/CS1 at 0x20000000
 247  * SDRAM on BR2/OR2/CS2 at 0x00000000
 248  * Free BR3/OR3/CS3
 249  * DSP1 on BR4/OR4/CS4 at 0x80000000
 250  * DSP2 on BR5/OR5/CS5 at 0xa0000000
 251  *
 252  * For now we just configure the Flash and the SDRAM and leave the others
 253  * untouched.
 254 */
 255
 256 #define CONFIG_SYS_FLASH_PROTECTION 0
 257
 258 #define FLASH_BASE0             0x40000000      /* FLASH bank #0        */
 259
 260 /* used to re-map FLASH both when starting from SRAM or FLASH:
 261  * restrict access enough to keep SRAM working (if any)
 262  * but not too much to meddle with FLASH accesses
 263  */
 264 #define CONFIG_SYS_OR_AM                0xff000000      /* OR addr mask */
 265 #define CONFIG_SYS_OR_ATM               0x00006000
 266
 267 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1        */
 268 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | \
 269                                  OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
 270
 271 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH)
 272 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
 273
 274 /*
 275  * BR2 and OR2 (SDRAM)
 276  *
 277  */
 278 #define SDRAM_BASE2                     0x00000000      /* SDRAM bank #0        */
 279 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 280
 281 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 282 #define CONFIG_SYS_OR_TIMING_SDRAM      ( 0x00000800 )
 283
 284 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
 285 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 286
 287 #define CONFIG_SYS_BR2                  CONFIG_SYS_BR2_PRELIM
 288 #define CONFIG_SYS_OR2                  CONFIG_SYS_OR2_PRELIM
 289
 290 /*
 291  * MAMR settings for SDRAM
 292  */
 293 #define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA |    MAMR_WLFA_1X | MAMR_RLFA_1X  \
 294                                         | MAMR_G0CLA_A11)
 295
 296 /*
 297  * Memory Periodic Timer Prescaler
 298  */
 299
 300 /* periodic timer for refresh */
 301 #define CONFIG_SYS_MAMR_PTA     0x0F000000
 302
 303 /*
 304    * BR4 and OR4 (DSP1)
 305    *
 306    * We do not wan't preliminary setup of the DSP, anyway we need the
 307    * UPMB setup correctly before we can access the DSP.
 308    *
 309 */
 310 #define DSP_BASE 0x80000000
 311
 312 #define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
 313 #define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
 314
 315 /*
 316  * Internal Definitions
 317  *
 318  * Boot Flags
 319  */
 320 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 321 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 322
 323 #endif  /* __CONFIG_H */