include/configs/FLAGADM.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  37 #define CONFIG_FLAGADM          1       /* ...on a FLAGA DM     */
  38 #define CONFIG_8xx_GCLK_FREQ 48000000   /*48MHz*/
  39
  40 #define CONFIG_SYS_TEXT_BASE    0x40000000
  41
  42 #undef  CONFIG_8xx_CONS_SMC1            /* Console is on SMC1           */
  43 #define CONFIG_8xx_CONS_SMC2    1
  44 #undef  CONFIG_8xx_CONS_NONE
  45
  46 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  47 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds     */
  48
  49 #undef  CONFIG_CLOCKS_IN_MHZ
  50
  51 #if 0
  52 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=bootp"
  53 #define CONFIG_BOOTCOMMAND                                                      \
  54    "setenv bootargs root=/dev/ram ip=off panic=1;"     \
  55    "bootm 40040000 400e0000"
  56 #else
  57 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=bootp panic=1"
  58 #define CONFIG_BOOTCOMMAND      "bootp 0x400000; bootm 0x400000"
  59 #endif /* 0|1*/
  60
  61 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  62 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  63
  64 /*#define       CONFIG_WATCHDOG*/       /* watchdog enabled             */
  65 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_SUBNETMASK
  71 #define CONFIG_BOOTP_GATEWAY
  72 #define CONFIG_BOOTP_HOSTNAME
  73 #define CONFIG_BOOTP_BOOTPATH
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75
  76
  77 /*
  78  * Command line configuration.
  79  */
  80
  81 #define CONFIG_CMD_BDI
  82 #define CONFIG_CMD_IMI
  83 #define CONFIG_CMD_CACHE
  84 #define CONFIG_CMD_MEMORY
  85 #define CONFIG_CMD_FLASH
  86 #define CONFIG_CMD_LOADB
  87 #define CONFIG_CMD_LOADS
  88 #define CONFIG_CMD_SAVEENV
  89 #define CONFIG_CMD_REGINFO
  90 #define CONFIG_CMD_IMMAP
  91 #define CONFIG_CMD_NET
  92
  93
  94 /*
  95  * Miscellaneous configurable options
  96  */
  97 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  98 #define CONFIG_SYS_PROMPT       "EEG> "         /* Monitor Command Prompt       */
  99 #if defined(CONFIG_CMD_KGDB)
 100 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 101 #else
 102 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 103 #endif
 104 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 105 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 106 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 107
 108 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 109 #define CONFIG_SYS_MEMTEST_END          0x0f00000       /* 1 ... 15 MB in DRAM  */
 110
 111 #define CONFIG_SYS_LOAD_ADDR            0x40040000      /* default load address */
 112
 113 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 114
 115 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 116
 117 /*
 118  * Low Level Configuration Settings
 119  * (address mappings, register initial values, etc.)
 120  * You should know what you are doing if you make changes here.
 121  */
 122 /*-----------------------------------------------------------------------
 123  * Internal Memory Mapped Register
 124  */
 125 #define CONFIG_SYS_IMMR         0xFF000000
 126
 127 /*-----------------------------------------------------------------------
 128  * Definitions for initial stack pointer and data area (in DPRAM)
 129  */
 130 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 131 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 132 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 133 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 134 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 135
 136 /*-----------------------------------------------------------------------
 137  * Start addresses for the final memory configuration
 138  * (Set up by the startup code)
 139  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 140  */
 141 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 142 #define CONFIG_SYS_FLASH_BASE           0x40000000
 143 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 145 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 146
 147 /*
 148  * For booting Linux, the board info and command line data
 149  * have to be in the first 8 MB of memory, since this is
 150  * the maximum mapped by the Linux kernel during initialization.
 151  */
 152 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 153
 154 /*-----------------------------------------------------------------------
 155  * FLASH organization
 156  */
 157 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 158 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip    */
 159
 160 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000    /* Timeout for Flash Erase (in ms)      */
 161 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 162
 163 #define CONFIG_ENV_IS_IN_FLASH  1
 164 /* This is a litlebit wasteful, but one sector is 128kb and we have to
 165  * assigne a whole sector for the environment, so that we can safely
 166  * erase and write it without disturbing the boot sector
 167  */
 168 #define CONFIG_ENV_OFFSET               0x20000 /*   Offset   of Environment Sector     */
 169 #define CONFIG_ENV_SIZE         0x20000 /* Total Size of Environment Sector     */
 170
 171 /*-----------------------------------------------------------------------
 172  * Cache Configuration
 173  */
 174 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 175 #if defined(CONFIG_CMD_KGDB)
 176 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 177 #endif
 178 #define CONFIG_SYS_DELAYED_ICACHE       1       /* enable ICache not before
 179                                                  * running in RAM.
 180                                                  */
 181
 182 /*-----------------------------------------------------------------------
 183  * SYPCR - System Protection Control                            11-9
 184  * SYPCR can only be written once after reset!
 185  *-----------------------------------------------------------------------
 186  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 187  */
 188 #ifdef CONFIG_WATCHDOG
 189 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
 190 #else
 191 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
 192 #endif
 193
 194 /*-----------------------------------------------------------------------
 195  * SIUMCR - SIU Module Configuration                            11-6
 196  *-----------------------------------------------------------------------
 197  * PCMCIA config., multi-function pin tri-state
 198  */
 199 #define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
 200                                                         SIUMCR_MLRC01 | SIUMCR_GB5E)
 201 #define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK)
 202
 203 /*-----------------------------------------------------------------------
 204  * TBSCR - Time Base Status and Control                         11-26
 205  *-----------------------------------------------------------------------
 206  * Clear Reference Interrupt Status, Timebase freezing enabled
 207  */
 208 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 209
 210 /*-----------------------------------------------------------------------
 211  * RTCSC - Real-Time Clock Status and Control Register          11-27
 212  *-----------------------------------------------------------------------
 213  */
 214 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 215
 216 /*-----------------------------------------------------------------------
 217  * PISCR - Periodic Interrupt Status and Control                11-31
 218  *-----------------------------------------------------------------------
 219  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 220  */
 221 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 222
 223 /*-----------------------------------------------------------------------
 224  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 225  *-----------------------------------------------------------------------
 226  * Reset PLL lock status sticky bit, timer expired status bit and timer
 227  * interrupt status bit miltiplier of 0x00b i.e. operation clock is
 228  * 4MHz * (0x00b+1) = 4MHz * 12 =  48MHz
 229  */
 230 #define CONFIG_SYS_PLPRCR       (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 231
 232 /*-----------------------------------------------------------------------
 233  * SCCR - System Clock and reset Control Register               15-27
 234  *-----------------------------------------------------------------------
 235  * Set clock output, timebase and RTC source and divider,
 236  * power management and some other internal clocks
 237  */
 238 #define SCCR_MASK       SCCR_EBDF11
 239 #define CONFIG_SYS_SCCR ( SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 240                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 241                          SCCR_DFALCD00)
 242
 243 #define CONFIG_SYS_DER 0
 244
 245 /*
 246  * In the Flaga DM we have:
 247  * Flash on BR0/OR0/CS0a at 0x40000000
 248  * Display on BR1/OR1/CS1 at 0x20000000
 249  * SDRAM on BR2/OR2/CS2 at 0x00000000
 250  * Free BR3/OR3/CS3
 251  * DSP1 on BR4/OR4/CS4 at 0x80000000
 252  * DSP2 on BR5/OR5/CS5 at 0xa0000000
 253  *
 254  * For now we just configure the Flash and the SDRAM and leave the others
 255  * untouched.
 256 */
 257
 258 #define CONFIG_SYS_FLASH_PROTECTION 0
 259
 260 #define FLASH_BASE0             0x40000000      /* FLASH bank #0        */
 261
 262 /* used to re-map FLASH both when starting from SRAM or FLASH:
 263  * restrict access enough to keep SRAM working (if any)
 264  * but not too much to meddle with FLASH accesses
 265  */
 266 #define CONFIG_SYS_OR_AM                0xff000000      /* OR addr mask */
 267 #define CONFIG_SYS_OR_ATM               0x00006000
 268
 269 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1        */
 270 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | \
 271                                  OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
 272
 273 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH)
 274 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
 275
 276 /*
 277  * BR2 and OR2 (SDRAM)
 278  *
 279  */
 280 #define SDRAM_BASE2                     0x00000000      /* SDRAM bank #0        */
 281 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 282
 283 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 284 #define CONFIG_SYS_OR_TIMING_SDRAM      ( 0x00000800 )
 285
 286 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
 287 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 288
 289 #define CONFIG_SYS_BR2                  CONFIG_SYS_BR2_PRELIM
 290 #define CONFIG_SYS_OR2                  CONFIG_SYS_OR2_PRELIM
 291
 292 /*
 293  * MAMR settings for SDRAM
 294  */
 295 #define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA |    MAMR_WLFA_1X | MAMR_RLFA_1X  \
 296                                         | MAMR_G0CLA_A11)
 297
 298 /*
 299  * Memory Periodic Timer Prescaler
 300  */
 301
 302 /* periodic timer for refresh */
 303 #define CONFIG_SYS_MAMR_PTA     0x0F000000
 304
 305 /*
 306    * BR4 and OR4 (DSP1)
 307    *
 308    * We do not wan't preliminary setup of the DSP, anyway we need the
 309    * UPMB setup correctly before we can access the DSP.
 310    *
 311 */
 312 #define DSP_BASE 0x80000000
 313
 314 #define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
 315 #define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
 316
 317 /*
 318  * Internal Definitions
 319  *
 320  * Boot Flags
 321  */
 322 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 323 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 324
 325 #endif  /* __CONFIG_H */