include/configs/FPS850L.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  37 #define CONFIG_FPS850L          1       /* ...on a FingerPrint Sensor   */
  38
  39 #undef  CONFIG_8xx_CONS_SMC1
  40 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  41 #undef  CONFIG_8xx_CONS_NONE
  42 #define CONFIG_BAUDRATE         19200
  43 #if 0
  44 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  45 #else
  46 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  47 #endif
  48 #define CONFIG_BOOTCOMMAND      "bootm 40020000" /* autoboot command    */
  49
  50 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  51
  52 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  53
  54 #define CONFIG_BOOTARGS         "root=/dev/nfs rw "                     \
  55                                 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "   \
  56                                 "nfsaddrs=10.0.0.99:10.0.0.2"
  57
  58 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  59 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  60
  61 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  62
  63
  64 /*
  65  * BOOTP options
  66  */
  67 #define CONFIG_BOOTP_SUBNETMASK
  68 #define CONFIG_BOOTP_GATEWAY
  69 #define CONFIG_BOOTP_HOSTNAME
  70 #define CONFIG_BOOTP_BOOTPATH
  71 #define CONFIG_BOOTP_BOOTFILESIZE
  72 #define CONFIG_BOOTP_SUBNETMASK
  73 #define CONFIG_BOOTP_GATEWAY
  74 #define CONFIG_BOOTP_HOSTNAME
  75 #define CONFIG_BOOTP_NISDOMAIN
  76 #define CONFIG_BOOTP_BOOTPATH
  77 #define CONFIG_BOOTP_DNS
  78 #define CONFIG_BOOTP_DNS2
  79 #define CONFIG_BOOTP_SEND_HOSTNAME
  80 #define CONFIG_BOOTP_NTPSERVER
  81 #define CONFIG_BOOTP_TIMEOFFSET
  82
  83
  84 /*
  85  * Command line configuration.
  86  */
  87 #include <config_cmd_default.h>
  88
  89 #undef CONFIG_CMD_CONSOLE
  90 #undef CONFIG_CMD_BDI
  91 #undef CONFIG_CMD_LOADS
  92 #undef CONFIG_CMD_LOADB
  93 #undef CONFIG_CMD_CACHE
  94
  95
  96 /*
  97  * Miscellaneous configurable options
  98  */
  99 #define CFG_LONGHELP                    /* undef to save memory         */
 100 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 101 #if defined(CONFIG_CMD_KGDB)
 102 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 103 #else
 104 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 105 #endif
 106 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 107 #define CFG_MAXARGS     16              /* max number of command args   */
 108 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 109
 110 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 111 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 112
 113 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 114
 115 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 116
 117 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 118
 119 /*
 120  * Low Level Configuration Settings
 121  * (address mappings, register initial values, etc.)
 122  * You should know what you are doing if you make changes here.
 123  */
 124 /*-----------------------------------------------------------------------
 125  * Internal Memory Mapped Register
 126  */
 127 #define CFG_IMMR                0xFFF00000
 128
 129 /*-----------------------------------------------------------------------
 130  * Definitions for initial stack pointer and data area (in DPRAM)
 131  */
 132 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 133 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 134 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 135 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 136 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 137
 138 /*-----------------------------------------------------------------------
 139  * Start addresses for the final memory configuration
 140  * (Set up by the startup code)
 141  * Please note that CFG_SDRAM_BASE _must_ start at 0
 142  */
 143 #define CFG_SDRAM_BASE          0x00000000
 144 #define CFG_FLASH_BASE          0x40000000
 145 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 146 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 147 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 148
 149 /*
 150  * For booting Linux, the board info and command line data
 151  * have to be in the first 8 MB of memory, since this is
 152  * the maximum mapped by the Linux kernel during initialization.
 153  */
 154 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 155
 156 /*-----------------------------------------------------------------------
 157  * FLASH organization
 158  */
 159 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 160 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip    */
 161
 162 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 163 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 164
 165 #define CFG_ENV_IS_IN_FLASH     1
 166 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 167 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 168
 169 /* Address and size of Redundant Environment Sector     */
 170 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 171 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 172
 173 /*-----------------------------------------------------------------------
 174  * Hardware Information Block
 175  */
 176 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 177 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 178 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 179
 180 /*-----------------------------------------------------------------------
 181  * Cache Configuration
 182  */
 183 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 184 #if defined(CONFIG_CMD_KGDB)
 185 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 186 #endif
 187
 188 /*-----------------------------------------------------------------------
 189  * SYPCR - System Protection Control                            11-9
 190  * SYPCR can only be written once after reset!
 191  *-----------------------------------------------------------------------
 192  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 193  */
 194 #if defined(CONFIG_WATCHDOG)
 195 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 196                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 197 #else
 198 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 199 #endif
 200
 201 /*-----------------------------------------------------------------------
 202  * SIUMCR - SIU Module Configuration                            11-6
 203  *-----------------------------------------------------------------------
 204  * PCMCIA config., multi-function pin tri-state
 205  */
 206 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 207
 208 /*-----------------------------------------------------------------------
 209  * TBSCR - Time Base Status and Control                         11-26
 210  *-----------------------------------------------------------------------
 211  * Clear Reference Interrupt Status, Timebase freezing enabled
 212  */
 213 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 214
 215 /*-----------------------------------------------------------------------
 216  * RTCSC - Real-Time Clock Status and Control Register          11-27
 217  *-----------------------------------------------------------------------
 218  */
 219 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 220
 221 /*-----------------------------------------------------------------------
 222  * PISCR - Periodic Interrupt Status and Control                11-31
 223  *-----------------------------------------------------------------------
 224  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 225  */
 226 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 227
 228 /*-----------------------------------------------------------------------
 229  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 230  *-----------------------------------------------------------------------
 231  * Reset PLL lock status sticky bit, timer expired status bit and timer
 232  * interrupt status bit - leave PLL multiplication factor unchanged !
 233  */
 234 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 235
 236 /*-----------------------------------------------------------------------
 237  * SCCR - System Clock and reset Control Register               15-27
 238  *-----------------------------------------------------------------------
 239  * Set clock output, timebase and RTC source and divider,
 240  * power management and some other internal clocks
 241  */
 242 #define SCCR_MASK       SCCR_EBDF11
 243 #define CFG_SCCR        (SCCR_TBS     | \
 244                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 245                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 246                          SCCR_DFALCD00)
 247
 248 /*-----------------------------------------------------------------------
 249  * PCMCIA stuff
 250  *-----------------------------------------------------------------------
 251  *
 252  */
 253 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 254 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 255 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 256 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 257 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 258 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 259 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 260 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 261
 262 /*-----------------------------------------------------------------------
 263  *
 264  *-----------------------------------------------------------------------
 265  *
 266  */
 267 #define CFG_DER 0
 268
 269 /*
 270  * Init Memory Controller:
 271  *
 272  * BR0/1 and OR0/1 (FLASH)
 273  */
 274
 275 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 276 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 277
 278 /* used to re-map FLASH both when starting from SRAM or FLASH:
 279  * restrict access enough to keep SRAM working (if any)
 280  * but not too much to meddle with FLASH accesses
 281  */
 282 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 283 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 284
 285 /*
 286  * FLASH timing:
 287  */
 288 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 289                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 290
 291 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 292 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 293 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 294
 295 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 296 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 297 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 298
 299 /*
 300  * BR2/3 and OR2/3 (SDRAM)
 301  *
 302  */
 303 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 304 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 305 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 306
 307 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 308 #define CFG_OR_TIMING_SDRAM     0x00000A00
 309
 310 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 311 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 312
 313 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 314 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 315
 316 /*
 317  * Memory Periodic Timer Prescaler
 318  *
 319  * The Divider for PTA (refresh timer) configuration is based on an
 320  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 321  * the number of chip selects (NCS) and the actually needed refresh
 322  * rate is done by setting MPTPR.
 323  *
 324  * PTA is calculated from
 325  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 326  *
 327  *      gclk      CPU clock (not bus clock!)
 328  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 329  *
 330  * 4096  Rows from SDRAM example configuration
 331  * 1000  factor s -> ms
 332  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 333  *    4  Number of refresh cycles per period
 334  *   64  Refresh cycle in ms per number of rows
 335  * --------------------------------------------
 336  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 337  *
 338  * 50 MHz => 50.000.000 / Divider =  98
 339  * 66 Mhz => 66.000.000 / Divider = 129
 340  * 80 Mhz => 80.000.000 / Divider = 156
 341  */
 342
 343 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
 344 #define CFG_MAMR_PTA    98
 345
 346 /*
 347  * For 16 MBit, refresh rates could be 31.3 us
 348  * (= 64 ms / 2K = 125 / quad bursts).
 349  * For a simpler initialization, 15.6 us is used instead.
 350  *
 351  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 352  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 353  */
 354 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 355 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 356
 357 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 358 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 359 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 360
 361 /*
 362  * MAMR settings for SDRAM
 363  */
 364
 365 /* 8 column SDRAM */
 366 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 367                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 368                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 369 /* 9 column SDRAM */
 370 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 371                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 372                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 373
 374
 375 /*
 376  * Internal Definitions
 377  *
 378  * Boot Flags
 379  */
 380 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 381 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 382
 383 #endif  /* __CONFIG_H */