include/configs/GENIETV.h

   1  /*
   2   * A collection of structures, addresses, and values associated with
   3   * the Motorola 860T FADS board.  Copied from the MBX stuff.
   4   * Magnus Damm added defines for 8xxrom and extended bd_info.
   5   * Helmut Buchsbaum added bitvalues for BCSRx
   6   *
   7   * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
   8   */
   9
  10 /*
  11  * The GENIETV is using the following physical memorymap (copied from
  12  * the FADS configuration):
  13  *
  14  * ff020000 -> ff02ffff : pcmcia
  15  * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxROM
  16  * ff000000 -> ff00ffff : IMAP       internal in the cpu
  17  * 30000000 -> 300fffff : flash      connected to CS0
  18  * 00000000 -> nnnnnnnn : sdram      setup by U-Boot
  19  *
  20  * CS pins are connected as follows:
  21  *
  22  * CS0 -512Kb boot flash
  23  * CS1 - SDRAM #1
  24  * CS2 - SDRAM #2
  25  * CS3 - Flash #1
  26  * CS4 - Flash #2
  27  * CS5 - Lon (if present)
  28  * CS6 - PCMCIA #1
  29  * CS7 - PCMCIA #2
  30  */
  31
  32 /* ------------------------------------------------------------------------- */
  33
  34 /*
  35  * board/config.h - configuration options, board specific
  36  */
  37
  38 #ifndef __CONFIG_H
  39 #define __CONFIG_H
  40
  41 #define CONFIG_SYS_TEXT_BASE    0x00000000
  42
  43 #define CONFIG_ETHADDR          08:00:22:50:70:63       /* Ethernet address */
  44 #define CONFIG_ENV_OVERWRITE    1       /* Overwrite the environment */
  45
  46 #define CONFIG_SYS_ALLOC_DPRAM                  /* Use dynamic DPRAM allocation */
  47
  48 #define CONFIG_SYS_AUTOLOAD             "n"     /* No autoload */
  49
  50 /*#define CONFIG_VIDEO          1       /  To enable the video initialization */
  51 /*#define CONFIG_VIDEO_ADDR     0x00200000 */
  52 /*#define CONFIG_HARD_I2C       1       /  I2C with hardware support */
  53 /*#define CONFIG_PCMCIA         1       /  To enable the PCMCIA initialization */
  54
  55 /*#define CONFIG_SYS_PCMCIA_IO_ADDR     0xff020000 */
  56 /*#define CONFIG_SYS_PCMCIA_IO_SIZE     0x10000 */
  57 /*#define CONFIG_SYS_PCMCIA_MEM_ADDR    0xe0000000 */
  58 /*#define CONFIG_SYS_PCMCIA_MEM_SIZE    0x10000 */
  59
  60 /* Video related */
  61
  62 /*#define CONFIG_VIDEO_LOGO                     1       /  Show the logo */
  63 /*#define CONFIG_VIDEO_ENCODER_AD7177           1       /  Enable this encoder */
  64 /*#define CONFIG_VIDEO_ENCODER_AD7177_ADDR      0xF4    /  ALSB to ground */
  65
  66 /* Wireless 56Khz 4PPM keyboard on SMCx */
  67
  68 /*#define CONFIG_KEYBOARD               0 */
  69 /*#define CONFIG_WL_4PPM_KEYBOARD_SMC   0       /  SMC to use (0 indexed) */
  70
  71 /*
  72  * High Level Configuration Options
  73  * (easy to change)
  74  */
  75 #include <mpc8xx_irq.h>
  76
  77 #define CONFIG_GENIETV          1
  78 #define CONFIG_MPC823           1
  79
  80 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  81 #undef  CONFIG_8xx_CONS_SMC2
  82 #undef  CONFIG_8xx_CONS_NONE
  83 #define CONFIG_BAUDRATE         9600
  84
  85 #define MPC8XX_FACT     12                      /* Multiply by 12       */
  86 #define MPC8XX_XIN      5000000                 /* 4 MHz clock          */
  87
  88 #define MPC8XX_HZ       ((MPC8XX_XIN) * (MPC8XX_FACT))
  89 #define CONFIG_SYS_PLPRCR_MF    ((MPC8XX_FACT-1) << 20)
  90 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_HZ       /* Force it - dont measure it */
  91
  92 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  93
  94 #if 1
  95 #define CONFIG_BOOTDELAY        1       /* autoboot after 2 seconds     */
  96 #define CONFIG_LOADS_ECHO       0       /* Dont echoes received characters */
  97 #define CONFIG_BOOTARGS         ""
  98 #define CONFIG_BOOTCOMMAND                                                      \
  99 "bootp; tftp; "                                                                 \
 100 "setenv bootargs console=tty0 console=ttyS0 "                                   \
 101 "root=/dev/nfs nfsroot=${serverip}:${rootpath} "                                \
 102 "ip=${ipaddr}:${serverip}:${gatewayip}:${subnetmask}:${hostname}:eth0:off ;"    \
 103 "bootm "
 104 #else
 105 #define CONFIG_BOOTDELAY        0       /* autoboot disabled            */
 106 #endif
 107
 108 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 109
 110
 111 /*
 112  * BOOTP options
 113  */
 114 #define CONFIG_BOOTP_BOOTFILESIZE
 115 #define CONFIG_BOOTP_BOOTPATH
 116 #define CONFIG_BOOTP_GATEWAY
 117 #define CONFIG_BOOTP_HOSTNAME
 118
 119
 120 /*
 121  * Command line configuration.
 122  */
 123 #include <config_cmd_default.h>
 124
 125
 126 /*
 127  * Miscellaneous configurable options
 128  */
 129 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 130 #define CONFIG_SYS_PROMPT               ":>"            /* Monitor Command Prompt       */
 131 #if defined(CONFIG_CMD_KGDB)
 132 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
 133 #else
 134 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 135 #endif
 136 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 137 #define CONFIG_SYS_MAXARGS              8               /* max number of command args   */
 138 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 139
 140 #define CONFIG_SYS_MEMTEST_START        0x00004000      /* memtest works on     */
 141 #define CONFIG_SYS_MEMTEST_END          0x00800000      /* 0 ... 8 MB in DRAM   */
 142
 143 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 144
 145 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 146
 147 #define CONFIG_SYS_BAUDRATE_TABLE       { 4800, 9600, 19200, 38400, 57600, 115200 }
 148
 149 /*
 150  * Low Level Configuration Settings
 151  * (address mappings, register initial values, etc.)
 152  * You should know what you are doing if you make changes here.
 153  */
 154 /*-----------------------------------------------------------------------
 155  * Internal Memory Mapped Register
 156  */
 157 #define CONFIG_SYS_IMMR         0xFF000000
 158 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
 159
 160 /*-----------------------------------------------------------------------
 161  * Definitions for initial stack pointer and data area (in DPRAM)
 162  */
 163 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 164 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 165 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 166 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 167
 168 /*-----------------------------------------------------------------------
 169  * Start addresses for the final memory configuration
 170  * (Set up by the startup code)
 171  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 172  * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
 173  */
 174 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 175 #define CONFIG_SYS_FLASH_BASE           0x02800000
 176 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 177 #if 0
 178 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 128 kB for Monitor   */
 179 #else
 180 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 512 kB for Monitor   */
 181 #endif
 182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 183 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 128 kB for malloc()  */
 184
 185 /*
 186  * For booting Linux, the board info and command line data
 187  * have to be in the first 8 MB of memory, since this is
 188  * the maximum mapped by the Linux kernel during initialization.
 189  */
 190 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 191 /*-----------------------------------------------------------------------
 192  * FLASH organization
 193  */
 194 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 195 #define CONFIG_SYS_MAX_FLASH_SECT       8       /* max number of sectors on one chip    */
 196
 197 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 198 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 199
 200 #define CONFIG_ENV_IS_IN_FLASH  1
 201 #define CONFIG_ENV_OFFSET               0x10000 /* Offset of Environment Sector         */
 202 #define CONFIG_ENV_SIZE         0x10000 /* Total Size of Environment Sector (64k)*/
 203
 204 /* values according to the manual */
 205
 206 /*-----------------------------------------------------------------------
 207  * Cache Configuration
 208  */
 209 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 210 #if defined(CONFIG_CMD_KGDB)
 211 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 212 #endif
 213
 214 /*-----------------------------------------------------------------------
 215  * SYPCR - System Protection Control                                    11-9
 216  * SYPCR can only be written once after reset!
 217  *-----------------------------------------------------------------------
 218  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 219  */
 220 #if defined(CONFIG_WATCHDOG)
 221 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 222                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 223 #else
 224 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 225 #endif
 226
 227 /*-----------------------------------------------------------------------
 228  * SIUMCR - SIU Module Configuration                                            11-6
 229  *-----------------------------------------------------------------------
 230  * PCMCIA config., multi-function pin tri-state
 231  *
 232 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 233  */
 234 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC10)
 235
 236 /*-----------------------------------------------------------------------
 237  * TBSCR - Time Base Status and Control                                 11-26
 238  *-----------------------------------------------------------------------
 239  * Clear Reference Interrupt Status, Timebase freezing enabled
 240  */
 241 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 242
 243 /*-----------------------------------------------------------------------
 244  * PISCR - Periodic Interrupt Status and Control                11-31
 245  *-----------------------------------------------------------------------
 246  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 247  */
 248 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 249
 250 /*-----------------------------------------------------------------------
 251  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 252  *-----------------------------------------------------------------------
 253  * Reset PLL lock status sticky bit, timer expired status bit and timer  *
 254  * interrupt status bit - leave PLL multiplication factor unchanged !
 255  *
 256  * #define CONFIG_SYS_PLPRCR    (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 257  */
 258 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF)
 259
 260 /*-----------------------------------------------------------------------
 261  * SCCR - System Clock and reset Control Register               15-27
 262  *-----------------------------------------------------------------------
 263  * Set clock output, timebase and RTC source and divider,
 264  * power management and some other internal clocks
 265  */
 266 #define SCCR_MASK       SCCR_EBDF11
 267 #define CONFIG_SYS_SCCR       (SCCR_TBS     | \
 268                                 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 269                                 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 270                                 SCCR_DFALCD00)
 271
 272 /*-----------------------------------------------------------------------
 273  *
 274  *-----------------------------------------------------------------------
 275  *
 276  */
 277 #define CONFIG_SYS_DER          0
 278
 279 /* Because of the way the 860 starts up and assigns CS0 the
 280 * entire address space, we have to set the memory controller
 281 * differently.  Normally, you write the option register
 282 * first, and then enable the chip select by writing the
 283 * base register.  For CS0, you must write the base register
 284 * first, followed by the option register.
 285 */
 286
 287 /*
 288  * Init Memory Controller:
 289  *
 290  * BR0 and OR0(FLASH)
 291  */
 292
 293 #define FLASH_BASE0_PRELIM      0x02800000      /* FLASH bank #0                */
 294
 295 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask         */
 296 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000      /* OR addr mask (512Kb) */
 297
 298 /* FLASH timing */
 299 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 300                                 OR_SCY_15_CLK | OR_TRLX )
 301
 302 /*#define CONFIG_SYS_OR0_REMAP  (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH) */
 303 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)          /* 0xfff80ff4 */
 304 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)     /* 0x02800401 */
 305
 306 /*
 307  * BR1/2 and OR1/2 (SDRAM)
 308 */
 309
 310 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 311
 312 #define SDRAM_MAX_SIZE          0x04000000      /* 64Mb bank */
 313 #define SDRAM_BASE1_PRELIM      0x00000000      /* First bank */
 314 #define SDRAM_BASE2_PRELIM      0x10000000      /* Second bank */
 315
 316 /*
 317  * Memory Periodic Timer Prescaler
 318  */
 319
 320 /* periodic timer for refresh */
 321 #define CONFIG_SYS_MBMR_PTB             0x5d            /* start with divider for 100 MHz       */
 322
 323 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 324 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 325 #define CONFIG_SYS_MPTPR_1BK_4K        MPTPR_PTP_DIV32
 326 /*
 327  * MBMR settings for SDRAM
 328  */
 329
 330 /* 8 column SDRAM */
 331 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
 332                         MAMR_G0CLA_A11 | MAMR_RLFA_1X | MAMR_WLFA_1X \
 333                         | MAMR_TLFA_4X) /* 0x5d802114 */
 334
 335 /* values according to the manual */
 336
 337 #define CONFIG_DRAM_50MHZ               1
 338 #define CONFIG_SDRAM_50MHZ
 339
 340 /* We don't use the 8259.
 341 */
 342 #define NR_8259_INTS    0
 343
 344 /*
 345  * MPC8xx CPM Options
 346  */
 347 #define CONFIG_SCC_ENET 1
 348
 349 #define CONFIG_DISK_SPINUP_TIME 1000000
 350
 351 /* PCMCIA configuration */
 352
 353 #define PCMCIA_MAX_SLOTS    1
 354 #define PCMCIA_SLOT_B 1
 355
 356 #endif  /* __CONFIG_H */