include/configs/HH405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2006
   9  * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41
  42 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  43 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  44 #define CONFIG_HH405            1       /* ...on a HH405 board          */
  45
  46 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  47
  48 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  49 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  50
  51 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  52
  53 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  54
  55 #define CONFIG_BAUDRATE         9600
  56 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  57
  58 #undef  CONFIG_BOOTARGS
  59 #undef  CONFIG_BOOTCOMMAND
  60
  61 #define CONFIG_PREBOOT          "autoupd"
  62
  63 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  64         "pciconfighost=1\0"                                             \
  65         ""
  66
  67 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  68
  69 #define CONFIG_PPC4xx_EMAC
  70 #undef  CONFIG_HAS_ETH1
  71
  72 #define CONFIG_MII              1       /* MII PHY management           */
  73 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  74 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  75 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  76
  77 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  78
  79 /*
  80  * Video console
  81  */
  82 #define CONFIG_VIDEO                    /* for sm501 video support      */
  83
  84 #ifdef CONFIG_VIDEO
  85 #define CONFIG_VIDEO_SM501
  86 #if 0
  87 #define CONFIG_VIDEO_SM501_32BPP
  88 #else
  89 #define CONFIG_VIDEO_SM501_16BPP
  90 #endif
  91 #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
  92 #define CONFIG_CFB_CONSOLE
  93 #define CONFIG_VIDEO_LOGO
  94 #define CONFIG_VGA_AS_SINGLE_DEVICE
  95 #define CONFIG_CONSOLE_EXTRA_INFO
  96 #define CONFIG_VIDEO_SW_CURSOR
  97 #define CONFIG_SPLASH_SCREEN
  98 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  99 #define CONFIG_SPLASH_SCREEN
 100 #define CONFIG_VIDEO_BMP_GZIP           /* gzip compressed bmp images   */
 101 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* for decompressed img */
 102
 103 #endif /* CONFIG_VIDEO */
 104
 105
 106 /*
 107  * BOOTP options
 108  */
 109 #define CONFIG_BOOTP_BOOTFILESIZE
 110 #define CONFIG_BOOTP_BOOTPATH
 111 #define CONFIG_BOOTP_GATEWAY
 112 #define CONFIG_BOOTP_HOSTNAME
 113
 114
 115 /*
 116  * Command line configuration.
 117  */
 118 #include <config_cmd_default.h>
 119
 120 #define CONFIG_CMD_DHCP
 121 #define CONFIG_CMD_PCI
 122 #define CONFIG_CMD_IRQ
 123 #define CONFIG_CMD_IDE
 124 #define CONFIG_CMD_FAT
 125 #define CONFIG_CMD_EXT2
 126 #define CONFIG_CMD_ELF
 127 #define CONFIG_CMD_NAND
 128 #define CONFIG_CMD_I2C
 129 #define CONFIG_CMD_DATE
 130 #define CONFIG_CMD_MII
 131 #define CONFIG_CMD_PING
 132 #define CONFIG_CMD_EEPROM
 133
 134 #ifdef CONFIG_VIDEO
 135 #define CONFIG_CMD_BMP
 136 #endif
 137
 138 #define CONFIG_MAC_PARTITION
 139 #define CONFIG_DOS_PARTITION
 140
 141 #define CONFIG_SUPPORT_VFAT
 142
 143 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
 144 #undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
 145
 146 #undef  CONFIG_BZIP2     /* include support for bzip2 compressed images */
 147 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 148
 149 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 150
 151 /*
 152  * Miscellaneous configurable options
 153  */
 154 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 155 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 156
 157 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 158
 159 #if defined(CONFIG_CMD_KGDB)
 160 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 161 #else
 162 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 163 #endif
 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 165 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 166 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 167
 168 #define CONFIG_SYS_DEVICE_NULLDEV      1       /* include nulldev device       */
 169
 170 #undef  CONFIG_SYS_CONSOLE_INFO_QUIET          /* print console @ startup       */
 171
 172 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 173
 174 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 175 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 176
 177 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 178 #define CONFIG_SYS_NS16550
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #define CONFIG_SYS_NS16550_REG_SIZE     1
 181 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 182
 183 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
 184 #define CONFIG_SYS_BASE_BAUD       691200
 185
 186 /* The following table includes the supported baudrates */
 187 #define CONFIG_SYS_BAUDRATE_TABLE      \
 188         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 189          57600, 115200, 230400, 460800, 921600 }
 190
 191 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 192 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 193
 194 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 195
 196 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 197
 198 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 199
 200 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 201
 202 /*-----------------------------------------------------------------------
 203  * RTC stuff
 204  *-----------------------------------------------------------------------
 205  */
 206 #define CONFIG_RTC_DS1338
 207 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 208
 209 /*-----------------------------------------------------------------------
 210  * NAND-FLASH stuff
 211  *-----------------------------------------------------------------------
 212  */
 213 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 214 #define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
 215 #define NAND_BIG_DELAY_US       25
 216
 217 #define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 218 #define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 219 #define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 220 #define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 221
 222 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 223 #define CONFIG_SYS_NAND_QUIET          1
 224
 225 /*-----------------------------------------------------------------------
 226  * PCI stuff
 227  *-----------------------------------------------------------------------
 228  */
 229 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 230 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 231 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 232
 233 #define CONFIG_PCI                      /* include pci support          */
 234 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 235 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 236 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 237                                         /* resource configuration       */
 238
 239 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 240
 241 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 242
 243 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 244 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 245 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 246 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 247 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 248 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 249 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 250 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 251 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 252
 253 /*-----------------------------------------------------------------------
 254  * IDE/ATA stuff
 255  *-----------------------------------------------------------------------
 256  */
 257 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 258 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 259 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 260
 261 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 262 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 263
 264 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 265 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 266
 267 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 268 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 269 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 270
 271 /*
 272  * For booting Linux, the board info and command line data
 273  * have to be in the first 8 MB of memory, since this is
 274  * the maximum mapped by the Linux kernel during initialization.
 275  */
 276 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 277 /*-----------------------------------------------------------------------
 278  * FLASH organization
 279  */
 280 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 281
 282 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 283 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 284
 285 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 286 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 287
 288 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 289 #define CONFIG_SYS_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 290 #define CONFIG_SYS_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 291 /*
 292  * The following defines are added for buggy IOP480 byte interface.
 293  * All other boards should use the standard values (CPCI405 etc.)
 294  */
 295 #define CONFIG_SYS_FLASH_READ0         0x0000  /* 0 is standard                        */
 296 #define CONFIG_SYS_FLASH_READ1         0x0001  /* 1 is standard                        */
 297 #define CONFIG_SYS_FLASH_READ2         0x0002  /* 2 is standard                        */
 298
 299 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 300
 301 #if 0 /* test-only */
 302 #define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 303 #define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
 304 #endif
 305
 306 /*-----------------------------------------------------------------------
 307  * Start addresses for the final memory configuration
 308  * (Set up by the startup code)
 309  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 310  */
 311 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 312 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 313 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 314 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor   */
 315 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)       /* Reserve 4 MB for malloc()    */
 316
 317 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 318 # define CONFIG_SYS_RAMBOOT             1
 319 #else
 320 # undef CONFIG_SYS_RAMBOOT
 321 #endif
 322
 323 /*-----------------------------------------------------------------------
 324  * Environment Variable setup
 325  */
 326 #define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 327 #define CONFIG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 328 #define CONFIG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
 329                                    /* total size of a CAT24WC16 is 2048 bytes */
 330
 331 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF4080000              /* NVRAM base address   */
 332 #define CONFIG_SYS_NVRAM_SIZE           0x8000                  /* NVRAM size           */
 333
 334 /*-----------------------------------------------------------------------
 335  * I2C EEPROM (CAT24WC16) for environment
 336  */
 337 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 338 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 339 #if 0 /* test-only */
 340 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 341 #else
 342 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 343 #endif
 344 #define CONFIG_SYS_I2C_SLAVE            0x7F
 345
 346 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24WC08             */
 347 #define CONFIG_SYS_EEPROM_WREN         1
 348
 349 #if 1 /* test-only */
 350 /* CAT24WC08/16... */
 351 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 352 /* mask of address bits that overflow into the "EEPROM chip address"    */
 353 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 354 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 355                                         /* 16 byte page write mode using*/
 356                                         /* last 4 bits of the address   */
 357 #else
 358 /* CAT24WC32/64... */
 359 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
 360 /* mask of address bits that overflow into the "EEPROM chip address"    */
 361 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 362 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* The Catalyst CAT24WC32 has   */
 363                                         /* 32 byte page write mode using*/
 364                                         /* last 5 bits of the address   */
 365 #endif
 366 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 367
 368 /*-----------------------------------------------------------------------
 369  * External Bus Controller (EBC) Setup
 370  */
 371
 372 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 373 #define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
 374 #define CONFIG_SYS_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
 375 #define CONFIG_SYS_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
 376
 377 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 378 #define CONFIG_SYS_EBC_PB0AP           0x92015480
 379 #define CONFIG_SYS_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 380
 381 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
 382 #define CONFIG_SYS_EBC_PB1AP           0x92015480
 383 #define CONFIG_SYS_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 384
 385 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 386 #define CONFIG_SYS_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 387 #define CONFIG_SYS_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 388
 389 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 390 #define CONFIG_SYS_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 391 #define CONFIG_SYS_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 392
 393 /* Memory Bank 4 (Epson LCD) initialization                                     */
 394 #define CONFIG_SYS_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
 395 #define CONFIG_SYS_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 396
 397 /*-----------------------------------------------------------------------
 398  * LCD Setup
 399  */
 400
 401 #define CONFIG_SYS_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
 402 #define CONFIG_SYS_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
 403 #define CONFIG_SYS_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
 404 #define CONFIG_SYS_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 405
 406 /*-----------------------------------------------------------------------
 407  * Universal Interrupt Controller (UIC) Setup
 408  */
 409
 410 /*
 411  * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
 412  */
 413 #define CONFIG_SYS_UIC0_POLARITY       (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
 414
 415 /*-----------------------------------------------------------------------
 416  * FPGA stuff
 417  */
 418
 419 #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
 420
 421 #define LCD_CLK_OFF             0x0000      /* Off                           */
 422 #define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
 423 #define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
 424 #define LCD_CLK_04165           0x3000      /* 4.165 MHz                     */
 425 #define LCD_CLK_06250           0x4000      /* 6.250 MHz                     */
 426 #define LCD_CLK_08330           0x5000      /* 8.330 MHz                     */
 427 #define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
 428 #define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */
 429
 430 #define CONFIG_SYS_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 431 #define CONFIG_SYS_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
 432
 433 /* FPGA program pin configuration */
 434 #define CONFIG_SYS_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 435 #define CONFIG_SYS_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 436 #define CONFIG_SYS_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 437 #define CONFIG_SYS_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 438 #define CONFIG_SYS_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 439
 440 /*-----------------------------------------------------------------------
 441  * Definitions for initial stack pointer and data area (in data cache)
 442  */
 443 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 444 #define CONFIG_SYS_TEMP_STACK_OCM        1
 445
 446 /* On Chip Memory location */
 447 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 448 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 449 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 450 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 451
 452 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 453 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 454
 455 /*-----------------------------------------------------------------------
 456  * Definitions for GPIO setup (PPC405EP specific)
 457  *
 458  * GPIO0[0]     - External Bus Controller BLAST output
 459  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 460  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 461  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 462  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 463  * GPIO0[24-27] - UART0 control signal inputs/outputs
 464  * GPIO0[28-29] - UART1 data signal input/output
 465  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 466  */
 467 #define CONFIG_SYS_GPIO0_OSRL           0x40000550
 468 #define CONFIG_SYS_GPIO0_OSRH           0x00000110
 469 #define CONFIG_SYS_GPIO0_ISR1L          0x00000000
 470 #define CONFIG_SYS_GPIO0_ISR1H          0x15555440
 471 #define CONFIG_SYS_GPIO0_TSRL           0x00000000
 472 #define CONFIG_SYS_GPIO0_TSRH           0x00000000
 473 #define CONFIG_SYS_GPIO0_TCR            0xF7FE0017
 474
 475 #define CONFIG_SYS_LCD_ENDIAN           (0x80000000 >> 7)
 476 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 8)   /* GPIO8 */
 477 #define CONFIG_SYS_TOUCH_RST            (0x80000000 >> 9)   /* GPIO9 */
 478 #define CONFIG_SYS_LCD0_RST             (0x80000000 >> 30)
 479 #define CONFIG_SYS_LCD1_RST             (0x80000000 >> 31)
 480
 481 /*
 482  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 483  * This value will be set if iic boot eprom is disabled.
 484  */
 485 #if 0
 486 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 487 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 488 #endif
 489 #if 0
 490 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 491 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 492 #endif
 493 #if 1
 494 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 495 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 496 #endif
 497
 498 #endif  /* __CONFIG_H */