include/configs/HH405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2006
   9  * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41
  42 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  43 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  44 #define CONFIG_HH405            1       /* ...on a HH405 board          */
  45
  46 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  47 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  48
  49 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  50
  51 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  52
  53 #define CONFIG_BAUDRATE         9600
  54 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  55
  56 #undef  CONFIG_BOOTARGS
  57 #undef  CONFIG_BOOTCOMMAND
  58
  59 #define CONFIG_PREBOOT          "autoupd"
  60
  61 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  62         "pciconfighost=1\0"                                             \
  63         ""
  64
  65 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  66
  67 #define CONFIG_NET_MULTI        1
  68 #undef  CONFIG_HAS_ETH1
  69
  70 #define CONFIG_MII              1       /* MII PHY management           */
  71 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  72 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  73 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  74
  75 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  76
  77 /*
  78  * Video console
  79  */
  80 #define CONFIG_VIDEO                    /* for sm501 video support      */
  81
  82 #ifdef CONFIG_VIDEO
  83 #define CONFIG_VIDEO_SM501
  84 #if 0
  85 #define CONFIG_VIDEO_SM501_32BPP
  86 #else
  87 #define CONFIG_VIDEO_SM501_16BPP
  88 #endif
  89 #define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
  90 #define CONFIG_CFB_CONSOLE
  91 #define CONFIG_VIDEO_LOGO
  92 #define CONFIG_VGA_AS_SINGLE_DEVICE
  93 #define CONFIG_CONSOLE_EXTRA_INFO
  94 #define CONFIG_VIDEO_SW_CURSOR
  95 #define CONFIG_SPLASH_SCREEN
  96 #define CFG_CONSOLE_IS_IN_ENV
  97 #define CONFIG_SPLASH_SCREEN
  98 #define CONFIG_VIDEO_BMP_GZIP           /* gzip compressed bmp images   */
  99 #define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20)       /* for decompressed img */
 100
 101 #endif /* CONFIG_VIDEO */
 102
 103
 104 /*
 105  * BOOTP options
 106  */
 107 #define CONFIG_BOOTP_BOOTFILESIZE
 108 #define CONFIG_BOOTP_BOOTPATH
 109 #define CONFIG_BOOTP_GATEWAY
 110 #define CONFIG_BOOTP_HOSTNAME
 111
 112
 113 /*
 114  * Command line configuration.
 115  */
 116 #include <config_cmd_default.h>
 117
 118 #define CONFIG_CMD_DHCP
 119 #define CONFIG_CMD_PCI
 120 #define CONFIG_CMD_IRQ
 121 #define CONFIG_CMD_IDE
 122 #define CONFIG_CMD_FAT
 123 #define CONFIG_CMD_EXT2
 124 #define CONFIG_CMD_ELF
 125 #define CONFIG_CMD_NAND
 126 #define CONFIG_CMD_I2C
 127 #define CONFIG_CMD_DATE
 128 #define CONFIG_CMD_MII
 129 #define CONFIG_CMD_PING
 130 #define CONFIG_CMD_EEPROM
 131
 132 #ifdef CONFIG_VIDEO
 133 #define CONFIG_CMD_BMP
 134 #endif
 135
 136 #define CONFIG_MAC_PARTITION
 137 #define CONFIG_DOS_PARTITION
 138
 139 #define CONFIG_SUPPORT_VFAT
 140
 141 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
 142 #undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
 143
 144 #undef  CONFIG_BZIP2     /* include support for bzip2 compressed images */
 145 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 146
 147 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 148
 149 /*
 150  * Miscellaneous configurable options
 151  */
 152 #define CFG_LONGHELP                    /* undef to save memory         */
 153 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 154
 155 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 156 #ifdef  CFG_HUSH_PARSER
 157 #define CFG_PROMPT_HUSH_PS2     "> "
 158 #endif
 159
 160 #if defined(CONFIG_CMD_KGDB)
 161 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 162 #else
 163 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 164 #endif
 165 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 166 #define CFG_MAXARGS     16              /* max number of command args   */
 167 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 168
 169 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 170
 171 #undef  CFG_CONSOLE_INFO_QUIET          /* print console @ startup      */
 172
 173 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 174
 175 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 176 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 177
 178 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 179 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 180 #define CFG_BASE_BAUD       691200
 181 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 182
 183 /* The following table includes the supported baudrates */
 184 #define CFG_BAUDRATE_TABLE      \
 185         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 186          57600, 115200, 230400, 460800, 921600 }
 187
 188 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 189 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 190
 191 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 192
 193 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 194
 195 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 196
 197 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 198
 199 /*-----------------------------------------------------------------------
 200  * RTC stuff
 201  *-----------------------------------------------------------------------
 202  */
 203 #define CONFIG_RTC_DS1338
 204 #define CFG_I2C_RTC_ADDR        0x68
 205
 206 /*-----------------------------------------------------------------------
 207  * NAND-FLASH stuff
 208  *-----------------------------------------------------------------------
 209  */
 210 #define CFG_NAND_BASE_LIST      { CFG_NAND_BASE }
 211 #define NAND_MAX_CHIPS          1
 212 #define CFG_MAX_NAND_DEVICE     1         /* Max number of NAND devices */
 213 #define NAND_BIG_DELAY_US       25
 214
 215 #define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 216 #define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 217 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 218 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 219
 220 #define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
 221
 222 /*-----------------------------------------------------------------------
 223  * PCI stuff
 224  *-----------------------------------------------------------------------
 225  */
 226 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 227 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 228 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 229
 230 #define CONFIG_PCI                      /* include pci support          */
 231 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 232 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 233                                         /* resource configuration       */
 234
 235 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 236
 237 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 238
 239 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 240 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 241 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 242 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 243 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 244 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 245 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 246 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 247 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 248
 249 /*-----------------------------------------------------------------------
 250  * IDE/ATA stuff
 251  *-----------------------------------------------------------------------
 252  */
 253 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 254 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 255 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 256
 257 #define CFG_IDE_MAXBUS          1               /* max. 1 IDE busses    */
 258 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 259
 260 #define CFG_ATA_BASE_ADDR       0xF0100000
 261 #define CFG_ATA_IDE0_OFFSET     0x0000
 262
 263 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
 264 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 265 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
 266
 267 /*
 268  * For booting Linux, the board info and command line data
 269  * have to be in the first 8 MB of memory, since this is
 270  * the maximum mapped by the Linux kernel during initialization.
 271  */
 272 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 273 /*-----------------------------------------------------------------------
 274  * FLASH organization
 275  */
 276 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 277
 278 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 279 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 280
 281 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 282 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 283
 284 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 285 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 286 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 287 /*
 288  * The following defines are added for buggy IOP480 byte interface.
 289  * All other boards should use the standard values (CPCI405 etc.)
 290  */
 291 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 292 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 293 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 294
 295 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 296
 297 #if 0 /* test-only */
 298 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 299 #define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
 300 #endif
 301
 302 /*-----------------------------------------------------------------------
 303  * Start addresses for the final memory configuration
 304  * (Set up by the startup code)
 305  * Please note that CFG_SDRAM_BASE _must_ start at 0
 306  */
 307 #define CFG_SDRAM_BASE          0x00000000
 308 #define CFG_FLASH_BASE          0xFFF80000
 309 #define CFG_MONITOR_BASE        TEXT_BASE
 310 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor   */
 311 #define CFG_MALLOC_LEN          (4 << 20)       /* Reserve 4 MB for malloc()    */
 312
 313 #if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
 314 # define CFG_RAMBOOT            1
 315 #else
 316 # undef CFG_RAMBOOT
 317 #endif
 318
 319 /*-----------------------------------------------------------------------
 320  * Environment Variable setup
 321  */
 322 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 323 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 324 #define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
 325                                    /* total size of a CAT24WC16 is 2048 bytes */
 326
 327 #define CFG_NVRAM_BASE_ADDR     0xF4080000              /* NVRAM base address   */
 328 #define CFG_NVRAM_SIZE          0x8000                  /* NVRAM size           */
 329
 330 /*-----------------------------------------------------------------------
 331  * I2C EEPROM (CAT24WC16) for environment
 332  */
 333 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 334 #if 0 /* test-only */
 335 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 336 #else
 337 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 338 #endif
 339 #define CFG_I2C_SLAVE           0x7F
 340
 341 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT24WC08             */
 342 #define CFG_EEPROM_WREN         1
 343
 344 #if 1 /* test-only */
 345 /* CAT24WC08/16... */
 346 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 347 /* mask of address bits that overflow into the "EEPROM chip address"    */
 348 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 349 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 350                                         /* 16 byte page write mode using*/
 351                                         /* last 4 bits of the address   */
 352 #else
 353 /* CAT24WC32/64... */
 354 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 355 /* mask of address bits that overflow into the "EEPROM chip address"    */
 356 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x01
 357 #define CFG_EEPROM_PAGE_WRITE_BITS 5    /* The Catalyst CAT24WC32 has   */
 358                                         /* 32 byte page write mode using*/
 359                                         /* last 5 bits of the address   */
 360 #endif
 361 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 362 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 363
 364 /*-----------------------------------------------------------------------
 365  * Cache Configuration
 366  */
 367 #define CFG_DCACHE_SIZE         16384   /* For AMCC 405 CPUs, older 405 ppc's    */
 368                                         /* have only 8kB, 16kB is save here     */
 369 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 370 #if defined(CONFIG_CMD_KGDB)
 371 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 372 #endif
 373
 374 /*-----------------------------------------------------------------------
 375  * External Bus Controller (EBC) Setup
 376  */
 377
 378 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 379 #define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
 380 #define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
 381 #define CFG_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
 382
 383 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 384 #define CFG_EBC_PB0AP           0x92015480
 385 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 386
 387 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
 388 #define CFG_EBC_PB1AP           0x92015480
 389 #define CFG_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
 390
 391 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
 392 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 393 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 394
 395 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
 396 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 397 #define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 398
 399 /* Memory Bank 4 (Epson LCD) initialization                                     */
 400 #define CFG_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
 401 #define CFG_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
 402
 403 /*-----------------------------------------------------------------------
 404  * LCD Setup
 405  */
 406
 407 #define CFG_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
 408 #define CFG_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
 409 #define CFG_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
 410 #define CFG_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
 411
 412 /*-----------------------------------------------------------------------
 413  * Universal Interrupt Controller (UIC) Setup
 414  */
 415
 416 /*
 417  * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
 418  */
 419 #define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_EXT6)
 420
 421 /*-----------------------------------------------------------------------
 422  * FPGA stuff
 423  */
 424
 425 #define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
 426
 427 /* FPGA internal regs */
 428 #define CFG_FPGA_CTRL           0x000
 429
 430 /* FPGA Control Reg */
 431 #define CFG_FPGA_CTRL_REV0      0x0001
 432 #define CFG_FPGA_CTRL_REV1      0x0002
 433 #define CFG_FPGA_CTRL_VGA0_BL   0x0004
 434 #define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
 435 #define CFG_FPGA_CTRL_CF_RESET  0x0040
 436 #define CFG_FPGA_CTRL_PS2_PWR   0x0080
 437 #define CFG_FPGA_CTRL_CF_PWRN   0x0100      /* low active                    */
 438 #define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
 439 #define CFG_FPGA_CTRL_LCD_CLK   0x7000      /* Mask for lcd clock            */
 440 #define CFG_FPGA_CTRL_OW_ENABLE 0x8000
 441
 442 #define CFG_FPGA_STATUS_CF_DETECT 0x8000
 443
 444 #define LCD_CLK_OFF             0x0000      /* Off                           */
 445 #define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
 446 #define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
 447 #define LCD_CLK_04165           0x3000      /* 4.165 MHz                     */
 448 #define LCD_CLK_06250           0x4000      /* 6.250 MHz                     */
 449 #define LCD_CLK_08330           0x5000      /* 8.330 MHz                     */
 450 #define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
 451 #define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */
 452
 453 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 454 #define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
 455
 456 /* FPGA program pin configuration */
 457 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 458 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 459 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 460 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 461 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 462
 463 /*-----------------------------------------------------------------------
 464  * Definitions for initial stack pointer and data area (in data cache)
 465  */
 466 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 467 #define CFG_TEMP_STACK_OCM        1
 468
 469 /* On Chip Memory location */
 470 #define CFG_OCM_DATA_ADDR       0xF8000000
 471 #define CFG_OCM_DATA_SIZE       0x1000
 472 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 473 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 474
 475 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 476 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 477 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 478
 479 /*-----------------------------------------------------------------------
 480  * Definitions for GPIO setup (PPC405EP specific)
 481  *
 482  * GPIO0[0]     - External Bus Controller BLAST output
 483  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 484  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 485  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 486  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 487  * GPIO0[24-27] - UART0 control signal inputs/outputs
 488  * GPIO0[28-29] - UART1 data signal input/output
 489  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 490  */
 491 #define CFG_GPIO0_OSRH          0x40000550
 492 #define CFG_GPIO0_OSRL          0x00000110
 493 #define CFG_GPIO0_ISR1H         0x00000000
 494 #define CFG_GPIO0_ISR1L         0x15555440
 495 #define CFG_GPIO0_TSRH          0x00000000
 496 #define CFG_GPIO0_TSRL          0x00000000
 497 #define CFG_GPIO0_TCR           0xF7FE0017
 498
 499 #define CFG_LCD_ENDIAN          (0x80000000 >> 7)
 500 #define CFG_EEPROM_WP           (0x80000000 >> 8)   /* GPIO8 */
 501 #define CFG_TOUCH_RST           (0x80000000 >> 9)   /* GPIO9 */
 502 #define CFG_LCD0_RST            (0x80000000 >> 30)
 503 #define CFG_LCD1_RST            (0x80000000 >> 31)
 504
 505 /*
 506  * Internal Definitions
 507  *
 508  * Boot Flags
 509  */
 510 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 511 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 512
 513 /*
 514  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 515  * This value will be set if iic boot eprom is disabled.
 516  */
 517 #if 0
 518 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 519 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 520 #endif
 521 #if 0
 522 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 523 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 524 #endif
 525 #if 1
 526 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 527 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 528 #endif
 529
 530 #endif  /* __CONFIG_H */