include/configs/HWW1U1A.h

   1 /*
   2  * Copyright 2009-2010 eXMeritus, A Boeing Company
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * HardwareWall HWW-1U-1A airborne unit configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /* High-level system configuration options */
  14 #define CONFIG_BOOKE            /* Power/PowerPC Book-E                 */
  15 #define CONFIG_E500             /* e500 (Power ISA v2.03 with SPE)      */
  16 #define CONFIG_MPC85xx          /* MPC8540/60/55/41/48 family           */
  17 #define CONFIG_FSL_ELBC         /* FreeScale Enhanced LocalBus Cntlr    */
  18 #define CONFIG_FSL_LAW          /* FreeScale Local Access Window        */
  19 #define CONFIG_P2020            /* FreeScale P2020                      */
  20 #define CONFIG_HWW1U1A          /* eXMeritus HardwareWall HWW-1U-1A     */
  21 #define CONFIG_MP               /* Multiprocessing support              */
  22 #define CONFIG_HWCONFIG         /* Use hwconfig from environment        */
  23
  24 #define CONFIG_L2_CACHE                 /* L2 cache enabled             */
  25 #define CONFIG_BTB                      /* Branch predition enabled     */
  26
  27 #define CONFIG_PANIC_HANG               /* No board reset on panic      */
  28 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_early_init_r()    */
  29 #define CONFIG_CMD_REGINFO              /* Dump various CPU regs        */
  30
  31 /*
  32  * Allow the use of 36-bit physical addresses.  Device-trees with 64-bit
  33  * addresses have known compatibility issues with some existing kernels.
  34  */
  35 #define CONFIG_ENABLE_36BIT_PHYS
  36 #define CONFIG_PHYS_64BIT
  37 #define CONFIG_ADDR_MAP
  38 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
  39
  40 /* Reserve plenty of RAM for malloc (we have 2GB+) */
  41 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  42
  43 /* How much L2 cache do we map so we can use it as RAM */
  44 #define CONFIG_SYS_INIT_RAM_LOCK
  45 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  46
  47 /* This is our temporary global data area just above the stack */
  48 #define CONFIG_SYS_GBL_DATA_OFFSET \
  49         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  50
  51 /* The stack grows down from the global data area */
  52 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  53
  54 /* Enable IRQs and watchdog with a 1000Hz system decrementer */
  55 #define CONFIG_CMD_IRQ
  56 #define CONFIG_SYS_HZ 1000
  57
  58
  59 /* -------------------------------------------------------------------- */
  60
  61 /*
  62  * Clock crystal configuration:
  63  *  (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
  64  *  (2) CCB: Multiplier from SYS_CLK
  65  *  (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
  66  */
  67 #define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
  68 #define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
  69
  70
  71 /* -------------------------------------------------------------------- */
  72
  73 /*
  74  * Memory map
  75  *
  76  * 0x0000_0000  0x7fff_ffff    2G  DDR2 ECC SDRAM
  77  * 0x8000_0000  0x9fff_ffff  512M  PCI-E Bus 1
  78  * 0xa000_0000  0xbfff_ffff  512M  PCI-E Bus 2 (unused)
  79  * 0xc000_0000  0xdfff_ffff  512M  PCI-E Bus 3
  80  * 0xe000_0000  0xe7ff_ffff  128M  Spansion FLASH
  81  * 0xe800_0000  0xefff_ffff  128M  Spansion FLASH
  82  * 0xffd0_0000  0xffd0_3fff   16K  L1 boot stack (TLB0)
  83  * 0xffe0_0000  0xffef_ffff    1M  CCSR
  84  * 0xffe0_5000  0xffe0_5fff    4K    Enhanced LocalBus Controller
  85  */
  86
  87 /* Virtual Memory Map */
  88 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  89 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  90 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
  91 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
  92 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
  93 #define CONFIG_SYS_FLASH_BASE           0xe0000000
  94 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
  95 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
  96 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
  97 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
  98 #define CONFIG_SYS_CCSRBAR              0xffe00000 /* CCSRBAR @ runtime */
  99
 100 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000 /* 512M */
 101 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000 /* 512M */
 102 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000 /* 512M */
 103 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000 /* 64k */
 104 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000 /* 64k */
 105 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000 /* 64k */
 106
 107 /* Physical Memory Map */
 108 #define CONFIG_SYS_PCIE3_MEM_PHYS     0xc00000000ull
 109 #define CONFIG_SYS_PCIE2_MEM_PHYS     0xc20000000ull
 110 #define CONFIG_SYS_PCIE1_MEM_PHYS     0xc40000000ull
 111 #define CONFIG_SYS_FLASH_BASE_PHYS    0xfe0000000ull
 112 #define CONFIG_SYS_PCIE3_IO_PHYS      0xfffc00000ull
 113 #define CONFIG_SYS_PCIE2_IO_PHYS      0xfffc10000ull
 114 #define CONFIG_SYS_PCIE1_IO_PHYS      0xfffc20000ull
 115 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
 116 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf          /* for ASM code */
 117 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xffd00000   /* for ASM code */
 118 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH       0xf          /* for ASM code */
 119 #define CONFIG_SYS_CCSRBAR_PHYS_LOW        0xffe00000   /* for ASM code */
 120
 121
 122 /* -------------------------------------------------------------------- */
 123
 124 /* U-Boot image (MONITOR_BASE == TEXT_BASE) */
 125 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc /* Top address in flash */
 126 #define CONFIG_SYS_TEXT_BASE            0xeff80000 /* Start of U-Boot image */
 127 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 128 #define CONFIG_SYS_MONITOR_LEN          0x80000 /* 512kB (4 flash sectors) */
 129
 130 /*
 131  * U-Boot Environment Image:  The two sectors immediately below U-Boot
 132  * form the U-Boot environment (regular and redundant).
 133  */
 134 #define CONFIG_ENV_IS_IN_FLASH  /* The environment image is stored in FLASH */
 135 #define CONFIG_ENV_OVERWRITE    /* Allow "protected" variables to be erased */
 136 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128kB (1 flash sector) */
 137 #define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 138 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR         - CONFIG_ENV_SECT_SIZE)
 139
 140 /* Only use 8kB of each environment sector for data */
 141 #define CONFIG_ENV_SIZE         0x2000 /* 8kB */
 142 #define CONFIG_ENV_SIZE_REDUND  0x2000 /* 8kB */
 143
 144
 145 /* -------------------------------------------------------------------- */
 146
 147 /* Serial Console Configuration */
 148 #define CONFIG_CONS_INDEX 1
 149 #define CONFIG_SYS_NS16550
 150 #define CONFIG_SYS_NS16550_SERIAL
 151 #define CONFIG_SYS_NS16550_REG_SIZE 1
 152 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
 153
 154 #define CONFIG_BAUDRATE 115200
 155 #define CONFIG_SYS_BAUDRATE_TABLE \
 156         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 157
 158 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 159 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 160
 161 /* Echo back characters received during a serial download */
 162 #define CONFIG_LOADS_ECHO
 163
 164 /* Allow a serial-download to temporarily change baud */
 165 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 166
 167
 168 /* -------------------------------------------------------------------- */
 169
 170 /* PCI and PCI-Express Support */
 171 #define CONFIG_PCI              /* Enable PCI/PCIE                      */
 172 #define CONFIG_PCI_PNP          /* Scan PCI busses                      */
 173 #define CONFIG_CMD_PCI          /* Enable the "pci" command             */
 174 #define CONFIG_FSL_PCI_INIT     /* Common FreeScale PCI initialization  */
 175 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 176 #define CONFIG_FSL_PCIE_RESET   /* We have PCI-E reset errata           */
 177 #define CONFIG_SYS_PCI_64BIT    /* PCI resources are 64-bit             */
 178 #define CONFIG_PCI_SCAN_SHOW    /* Display PCI scan during boot         */
 179
 180 /* Enable 2 of the 3 PCI-E controllers */
 181 #define CONFIG_PCIE3
 182 #undef  CONFIG_PCIE2
 183 #define CONFIG_PCIE1
 184
 185 /* Display human-readable names when initializing */
 186 #define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
 187 #define CONFIG_SYS_PCIE2_NAME "Unused"
 188 #define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
 189
 190 /*
 191  * PCI bus addresses
 192  * Memory space is mapped 1-1, but I/O space must start from 0.
 193  */
 194 #define CONFIG_SYS_PCIE3_IO_BUS  0x00000000
 195 #define CONFIG_SYS_PCIE2_IO_BUS  0x00000000
 196 #define CONFIG_SYS_PCIE1_IO_BUS  0x00000000
 197 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
 198 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
 199 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
 200
 201
 202 /* -------------------------------------------------------------------- */
 203
 204 /* Generic FreeScale hardware I2C support */
 205 #define CONFIG_HARD_I2C
 206 #define CONFIG_FSL_I2C
 207 #define CONFIG_CMD_I2C
 208 #define CONFIG_I2C_MULTI_BUS
 209 #define CONFIG_SYS_I2C_OFFSET  0x3000
 210 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 211
 212 /* I2C bus configuration */
 213 #define CONFIG_SYS_I2C_SPEED 400000
 214 #define CONFIG_SYS_I2C_SLAVE 0x7F
 215
 216 /* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
 217 #define CONFIG_SYS_SPD_BUS_NUM 0
 218 #define SPD_EEPROM_ADDRESS 0x51
 219
 220 /* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
 221 #define CONFIG_CMD_DATE
 222 #define CONFIG_RTC_DS1337
 223 #define CONFIG_SYS_RTC_BUS_NUM 0
 224 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 225 /* Turn off RTC square-wave output to save battery */
 226 #define CONFIG_SYS_RTC_DS1337_NOOSC
 227
 228 /*
 229  * AT24C128N EEPROM at I2C0-0x53.
 230  *
 231  * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages
 232  * of 64 bytes per page.  The chip uses 2-byte addresses and has a max write
 233  * cycle time of 20ms according to the datasheet.
 234  *
 235  * NOTE: Our environment is stored on regular direct-attached FLASH, this
 236  * chip is only used as a write-protected backup for certain key settings
 237  * such as the serial# and macaddr values.  (EG: "env import")
 238  */
 239 #define CONFIG_CMD_EEPROM
 240 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 241 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
 242 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 243 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */
 244 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
 245
 246 /*
 247  * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554).  You
 248  * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command
 249  * will not be able to access the chip.
 250  */
 251 #define CONFIG_PCA953X
 252 #define CONFIG_CMD_PCA953X
 253 #define CONFIG_CMD_PCA953X_INFO
 254 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
 255
 256
 257 /* -------------------------------------------------------------------- */
 258
 259 /* FreeScale DDR2/3 SDRAM Controller */
 260 #define CONFIG_FSL_DDR2         /* Our SDRAM slot is DDR2               */
 261 #define CONFIG_DDR_ECC          /* Enable ECC by default                */
 262 #define CONFIG_DDR_SPD          /* Detect DDR config from SPD EEPROM    */
 263 #define CONFIG_SPD_EEPROM       /* ...why 2 config variables for this?  */
 264 #define CONFIG_VERY_BIG_RAM     /* Allow 2GB+ of RAM                    */
 265 #define CONFIG_CMD_SDRAM
 266
 267 /* Standard P2020 DDR controller parameters */
 268 #define CONFIG_NUM_DDR_CONTROLLERS 1
 269 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
 270 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
 271
 272 /* Make sure to tell the DDR controller to preinitialze all of RAM */
 273 #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
 274 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 275
 276
 277 /* -------------------------------------------------------------------- */
 278
 279 /* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
 280 #define CONFIG_FLASH_CFI_DRIVER
 281 #define CONFIG_SYS_FLASH_CFI
 282 #define CONFIG_SYS_FLASH_EMPTY_INFO
 283 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 284
 285 /* Flash banks (2x 128MB) */
 286 #define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
 287 #define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
 288 #define CONFIG_SYS_MAX_FLASH_BANKS 2
 289 #define CONFIG_SYS_MAX_FLASH_SECT 1024
 290 #define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
 291
 292 /*
 293  * Flash access modes and timings (values are the defaults after a RESET).
 294  *
 295  * NOTE: These could probably be optimized but are more than sufficient for
 296  * this particular system for the moment.
 297  */
 298 #define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
 299 #define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
 300                 | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 301
 302 /* Configure both flash banks */
 303 #define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
 304 #define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
 305 #define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
 306 #define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
 307
 308 /* Flash timeouts (in ms) */
 309 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s)      */
 310 #define CONFIG_SYS_FLASH_WRITE_TOUT   500UL /* Write (0.5s)     */
 311
 312 /* Quiet flash testing */
 313 #define CONFIG_SYS_FLASH_QUIET_TEST
 314
 315 /* Make program/erase count down from 45/5 (9....8....7....) */
 316 #define CONFIG_FLASH_SHOW_PROGRESS 45
 317
 318
 319 /* -------------------------------------------------------------------- */
 320
 321 /* Ethernet Device Support */
 322 #define CONFIG_MII                      /* Enable MII PHY code          */
 323 #define CONFIG_MII_DEFAULT_TSEC         /* ??? Copied from P2020DS      */
 324 #define CONFIG_PHY_GIGE                 /* Support Gigabit PHYs         */
 325 #define CONFIG_ETHPRIME "e1000#0"       /* Default to external ports    */
 326
 327 /* Turn on various helpful networking commands */
 328 #define CONFIG_CMD_DHCP
 329 #define CONFIG_CMD_MII
 330 #define CONFIG_CMD_NET
 331 #define CONFIG_CMD_PING
 332
 333 /* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
 334 #define CONFIG_TSEC_ENET
 335 #define CONFIG_TSEC1
 336 #define CONFIG_TSEC2
 337 #define CONFIG_TSEC3
 338 #define CONFIG_TSEC1_NAME "owt0"
 339 #define CONFIG_TSEC2_NAME "owt1"
 340 #define CONFIG_TSEC3_NAME "peer"
 341 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
 342 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
 343 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
 344 #define TSEC1_PHYIDX 0
 345 #define TSEC2_PHYIDX 0
 346 #define TSEC3_PHYIDX 0
 347 #define TSEC1_PHY_ADDR      2
 348 #define TSEC2_PHY_ADDR      3
 349 #define TSEC3_PHY_ADDR      4
 350 #define TSEC3_PHY_ADDR_CPUA 4
 351 #define TSEC3_PHY_ADDR_CPUB 5
 352
 353 /* PCI-E dual-port E1000 (external ethernet ports) */
 354 #define CONFIG_E1000
 355 #define CONFIG_E1000_SPI
 356 #define CONFIG_E1000_SPI_GENERIC
 357 #define CONFIG_CMD_E1000
 358
 359 /* We need the SPI infrastructure to poke the E1000's EEPROM */
 360 #define CONFIG_SPI
 361 #define CONFIG_SPI_X
 362 #define CONFIG_CMD_SPI
 363 #define MAX_SPI_BYTES 32
 364
 365
 366 /* -------------------------------------------------------------------- */
 367
 368 /* USB Thumbdrive Device Support */
 369 #define CONFIG_USB_EHCI
 370 #define CONFIG_USB_EHCI_FSL
 371 #define CONFIG_USB_STORAGE
 372 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 373 #define CONFIG_CMD_USB
 374
 375 /* Partition and Filesystem support */
 376 #define CONFIG_DOS_PARTITION
 377 #define CONFIG_EFI_PARTITION
 378 #define CONFIG_ISO_PARTITION
 379 #define CONFIG_CMD_EXT2
 380 #define CONFIG_CMD_FAT
 381
 382
 383 /* -------------------------------------------------------------------- */
 384
 385 /* Command line configuration. */
 386 #define CONFIG_CMDLINE_EDITING          /* Enable command editing       */
 387 #define CONFIG_COMMAND_HISTORY          /* Enable command history       */
 388 #define CONFIG_AUTO_COMPLETE            /* Enable command completion    */
 389 #define CONFIG_SYS_LONGHELP             /* Enable detailed command help */
 390 #define CONFIG_SYS_MAXARGS 128          /* Up to 128 command-line args  */
 391 #define CONFIG_SYS_PBSIZE 8192          /* Allow up to 8k printed lines */
 392 #define CONFIG_SYS_CBSIZE 4096          /* Allow up to 4k command lines */
 393 #define CONFIG_SYS_BARGSIZE 4096        /* Allow up to 4k boot args     */
 394 #define CONFIG_SYS_HUSH_PARSER          /* Enable a fancier shell       */
 395
 396 /* A little extra magic here for the prompt */
 397 #define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
 398 #ifndef __ASSEMBLY__
 399 const char *hww1u1a_get_ps1(void);
 400 #endif
 401
 402 /* Include a bunch of default commands we probably want */
 403 #include <config_cmd_default.h>
 404
 405 /* Other helpful shell-like commands */
 406 #define CONFIG_MD5
 407 #define CONFIG_SHA1
 408 #define CONFIG_CMD_MD5SUM
 409 #define CONFIG_CMD_SHA1SUM
 410 #define CONFIG_CMD_ASKENV
 411 #define CONFIG_CMD_SETEXPR
 412
 413
 414 /* -------------------------------------------------------------------- */
 415
 416 /* Image manipulation and booting */
 417
 418 /* We use the OpenFirmware-esque "Flattened Device Tree" */
 419 #define CONFIG_OF_LIBFDT
 420 #define CONFIG_OF_BOARD_SETUP
 421 #define CONFIG_OF_STDOUT_VIA_ALIAS
 422
 423 /*
 424  * For booting Linux, the board info and command line data
 425  * have to be in the first 64 MB of memory, since this is
 426  * the maximum mapped by the Linux kernel during initialization.
 427  */
 428 #define CONFIG_CMD_ELF
 429 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map    */
 430 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB  */
 431
 432 /* This is the default address for commands with an optional address arg */
 433 #define CONFIG_LOADADDR           100000
 434 #define CONFIG_SYS_LOAD_ADDR    0x100000
 435
 436 /* Test memory starting from the default load address to just below 2GB */
 437 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_LOAD_ADDR
 438 #define CONFIG_SYS_MEMTEST_END          0x7f000000
 439
 440 #define CONFIG_BOOTDELAY 20
 441 #define CONFIG_BOOTCOMMAND "echo Not yet flashed"
 442 #define CONFIG_BOOTARGS ""
 443 #define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
 444
 445 /* Extra environment parameters */
 446 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 447         "ethprime=e1000#0\0"                                            \
 448         "ethrotate=no\0"                                                \
 449         "setbootargs=setenv bootargs "                                  \
 450                         "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0"   \
 451         "perf_mode=performance\0"                                       \
 452         "hwconfig="     "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"   \
 453                         "usb1:dr_mode=host,phy_type=ulpi\0"             \
 454         "flkernel=0xe8000000\0"                                         \
 455         "flinitramfs=0xe8800000\0"                                      \
 456         "fldevicetree=0xeff20000\0"                                     \
 457         "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0"    \
 458         "flboot=run preboot; run flbootm\0"                             \
 459         "restore_eeprom=i2c dev 0 && "                                  \
 460                         "eeprom read $loadaddr 0x0000 0x2000 && "       \
 461                         "env import -c $loadaddr 0x2000\0"
 462
 463 #endif  /* __CONFIG_H */