include/configs/ICU862.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #include <mpc8xx_irq.h>
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_MPC860           1
  22 #define CONFIG_MPC860T          1
  23 #define CONFIG_ICU862           1
  24 #define CONFIG_MPC862           1
  25
  26 #define CONFIG_SYS_TEXT_BASE    0x40F00000
  27
  28 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  29 #undef  CONFIG_8xx_CONS_SMC2
  30 #undef  CONFIG_8xx_CONS_NONE
  31 #define CONFIG_BAUDRATE         9600
  32 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  33
  34 #ifdef CONFIG_100MHz
  35 #define MPC8XX_FACT             24              /* Multiply by 24       */
  36 #define MPC8XX_XIN              4165000         /* 4.165 MHz in         */
  37 #define CONFIG_8xx_GCLK_FREQ    (MPC8XX_FACT * MPC8XX_XIN)
  38                                     /* define if cant' use get_gclk_freq */
  39 #else
  40 #if 1                           /* for 50MHz version of processor       */
  41 #define MPC8XX_FACT             12              /* Multiply by 12       */
  42 #define MPC8XX_XIN              4000000         /* 4 MHz in             */
  43 #define CONFIG_8xx_GCLK_FREQ    48000000 /* define if cant use get_gclk_freq */
  44 #else                           /* for 80MHz version of processor       */
  45 #define MPC8XX_FACT             20              /* Multiply by 20       */
  46 #define MPC8XX_XIN              4000000         /* 4 MHz in             */
  47 #define CONFIG_8xx_GCLK_FREQ    80000000 /* define if cant use get_gclk_freq */
  48 #endif
  49 #endif
  50
  51 #if 0
  52 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  53 #else
  54 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  55 #endif
  56
  57 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  58
  59 #undef  CONFIG_BOOTARGS
  60 #define CONFIG_BOOTCOMMAND                                                      \
  61         "bootp;"                                                                \
  62         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  63         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  64         "bootm"
  65
  66 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  67
  68 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_SUBNETMASK
  74 #define CONFIG_BOOTP_GATEWAY
  75 #define CONFIG_BOOTP_HOSTNAME
  76 #define CONFIG_BOOTP_BOOTPATH
  77 #define CONFIG_BOOTP_BOOTFILESIZE
  78
  79
  80 #undef  CONFIG_SCC1_ENET                /* disable SCC1 ethernet */
  81 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
  82 #define CONFIG_MII              1
  83 #if 1
  84 #define CONFIG_SYS_DISCOVER_PHY 1
  85 #else
  86 #undef  CONFIG_SYS_DISCOVER_PHY
  87 #endif
  88
  89 #define CONFIG_MAC_PARTITION
  90 #define CONFIG_DOS_PARTITION
  91
  92 /* enable I2C and select the hardware/software driver */
  93 #define CONFIG_SYS_I2C
  94 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
  95 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
  96 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
  97 /*
  98  * Software (bit-bang) I2C driver configuration
  99  */
 100 #define PB_SCL          0x00000020      /* PB 26 */
 101 #define PB_SDA          0x00000010      /* PB 27 */
 102
 103 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 104 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 105 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 106 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 107 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 108                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 109 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 110                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 111 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 112
 113 #define CONFIG_SYS_EEPROM_X40430                /* Use a Xicor X40430 EEPROM    */
 114 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  4    /* 16 bytes page write mode     */
 115
 116 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 117
 118 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 119 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 120
 121
 122 /*
 123  * Command line configuration.
 124  */
 125 #include <config_cmd_default.h>
 126
 127 #define CONFIG_CMD_ASKENV
 128 #define CONFIG_CMD_DATE
 129 #define CONFIG_CMD_DHCP
 130 #define CONFIG_CMD_EEPROM
 131 #define CONFIG_CMD_I2C
 132 #define CONFIG_CMD_IDE
 133 #define CONFIG_CMD_NFS
 134 #define CONFIG_CMD_SNTP
 135
 136
 137 /*
 138  * Miscellaneous configurable options
 139  */
 140 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 141 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 142 #if defined(CONFIG_CMD_KGDB)
 143 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 144 #else
 145 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 146 #endif
 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 148 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 149 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 150
 151 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 152 #define CONFIG_SYS_MEMTEST_END          0x0400000       /* 1 ... 4 MB in DRAM   */
 153
 154 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 155
 156 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 157
 158 /*
 159  * Low Level Configuration Settings
 160  * (address mappings, register initial values, etc.)
 161  * You should know what you are doing if you make changes here.
 162  */
 163 /*-----------------------------------------------------------------------
 164  * Internal Memory Mapped Register
 165  */
 166 #define CONFIG_SYS_IMMR         0xF0000000
 167 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
 168
 169 /*-----------------------------------------------------------------------
 170  * Definitions for initial stack pointer and data area (in DPRAM)
 171  */
 172 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 173 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 174 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 175 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 176
 177 /*-----------------------------------------------------------------------
 178  * Start addresses for the final memory configuration
 179  * (Set up by the startup code)
 180  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 181  */
 182 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 183 #define CONFIG_SYS_FLASH_BASE           0x40000000
 184 #define CONFIG_SYS_FLASH_SIZE           ((uint)(16 * 1024 * 1024))      /* max 16Mbyte */
 185
 186 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 187
 188 #if 0
 189 #if defined(DEBUG)
 190 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 191 #else
 192 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 193 #endif
 194 #else
 195 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
 196 #endif
 197 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 198 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 199
 200 /*
 201  * For booting Linux, the board info and command line data
 202  * have to be in the first 8 MB of memory, since this is
 203  * the maximum mapped by the Linux kernel during initialization.
 204  */
 205 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 206 /*-----------------------------------------------------------------------
 207  * FLASH organization
 208  */
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 210 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max number of sectors on one chip    */
 211
 212 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 213 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Timeout for Flash Write (in ms)      */
 214
 215
 216 #define CONFIG_ENV_IS_IN_FLASH  1
 217 #define CONFIG_ENV_OFFSET               0x00F40000
 218
 219 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment sector     */
 220 #define CONFIG_ENV_SIZE         0x4000  /* Used Size of Environment Sector      */
 221 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 222
 223 /*-----------------------------------------------------------------------
 224  * Cache Configuration
 225  */
 226 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 227 #if defined(CONFIG_CMD_KGDB)
 228 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 229 #endif
 230
 231 /*-----------------------------------------------------------------------
 232  * SYPCR - System Protection Control                                    11-9
 233  * SYPCR can only be written once after reset!
 234  *-----------------------------------------------------------------------
 235  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 236  */
 237 #if defined(CONFIG_WATCHDOG)
 238 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 239                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 240 #else
 241 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 242 #endif
 243
 244 /*-----------------------------------------------------------------------
 245  * SIUMCR - SIU Module Configuration                                    11-6
 246  *-----------------------------------------------------------------------
 247  * PCMCIA config., multi-function pin tri-state
 248  */
 249 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 250
 251 /*-----------------------------------------------------------------------
 252  * TBSCR - Time Base Status and Control                                 11-26
 253  *-----------------------------------------------------------------------
 254  * Clear Reference Interrupt Status, Timebase freezing enabled
 255  */
 256 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 257
 258 /*-----------------------------------------------------------------------
 259  * PISCR - Periodic Interrupt Status and Control                11-31
 260  *-----------------------------------------------------------------------
 261  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 262  */
 263 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 264
 265 /*-----------------------------------------------------------------------
 266  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 267  *-----------------------------------------------------------------------
 268  * set the PLL, the low-power modes and the reset control (15-29)
 269  */
 270 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 271                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 272
 273 /*-----------------------------------------------------------------------
 274  * SCCR - System Clock and reset Control Register               15-27
 275  *-----------------------------------------------------------------------
 276  * Set clock output, timebase and RTC source and divider,
 277  * power management and some other internal clocks
 278  */
 279 #ifdef CONFIG_100MHz    /* for 100 MHz, external bus is half CPU clock */
 280 #define SCCR_MASK       0
 281 #define CONFIG_SYS_SCCR (SCCR_TBS       | SCCR_COM00    | SCCR_DFSYNC00 | \
 282                          SCCR_DFBRG00   | SCCR_DFNL000  | SCCR_DFNH000  | \
 283                          SCCR_DFLCD000  |SCCR_DFALCD00  | SCCR_EBDF01)
 284 #else                   /* up to 50 MHz we use a 1:1 clock */
 285 #define SCCR_MASK       SCCR_EBDF11
 286 #define CONFIG_SYS_SCCR (SCCR_TBS       | SCCR_COM00    | SCCR_DFSYNC00 | \
 287                          SCCR_DFBRG00   | SCCR_DFNL000  | SCCR_DFNH000  | \
 288                          SCCR_DFLCD000  |SCCR_DFALCD00  )
 289 #endif  /* CONFIG_100MHz */
 290
 291 /*-----------------------------------------------------------------------
 292  * RCCR - RISC Controller Configuration Register                19-4
 293  *-----------------------------------------------------------------------
 294  */
 295 /* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
 296 #define CONFIG_SYS_RCCR 0x0020
 297
 298 /*-----------------------------------------------------------------------
 299  * PCMCIA stuff
 300  *-----------------------------------------------------------------------
 301  */
 302 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 303 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 304 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 305 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 306 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 307 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 308 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 309 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 310
 311 /*-----------------------------------------------------------------------
 312  * PCMCIA Power Switch
 313  *
 314  * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
 315  * control the voltages on the PCMCIA slot which is connected to Port B
 316  *-----------------------------------------------------------------------
 317  */
 318                         /* Output pins */
 319 #define TPS2205_VCC5    0x00008000      /* PB.16:  5V Voltage Control   */
 320 #define TPS2205_VCC3    0x00004000      /* PB.17:  3V Voltage Control   */
 321 #define TPS2205_VPP_PGM 0x00002000      /* PB.18: PGM Voltage Control   */
 322 #define TPS2205_VPP_VCC 0x00001000      /* PB.19: VPP Voltage Control   */
 323 #define TPS2205_SHDN    0x00000200      /* PB.22: Shutdown              */
 324 #define TPS2205_OUTPUTS ( TPS2205_VCC5    | TPS2205_VCC3    | \
 325                           TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
 326                           TPS2205_SHDN)
 327
 328                         /* Input pins */
 329 #define TPS2205_OC      0x00000100      /* PB.23: Over-Current          */
 330 #define TPS2205_INPUTS  ( TPS2205_OC )
 331
 332 /*-----------------------------------------------------------------------
 333  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 334  *-----------------------------------------------------------------------
 335  */
 336
 337 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 338 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 339
 340 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 341 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 342 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 343
 344 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 345 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 346
 347 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 348
 349 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 350
 351 /* Offset for data I/O                  */
 352 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 353
 354 /* Offset for normal register accesses  */
 355 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 356
 357 /* Offset for alternate registers       */
 358 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 359
 360
 361  /*-----------------------------------------------------------------------
 362  *
 363  *-----------------------------------------------------------------------
 364  *
 365  */
 366 #define CONFIG_SYS_DER          0
 367
 368 /* Because of the way the 860 starts up and assigns CS0 the
 369 * entire address space, we have to set the memory controller
 370 * differently.  Normally, you write the option register
 371 * first, and then enable the chip select by writing the
 372 * base register.  For CS0, you must write the base register
 373 * first, followed by the option register.
 374 */
 375
 376 /*
 377  * Init Memory Controller:
 378  *
 379  * BR0 and OR0 (FLASH)
 380  */
 381
 382 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 383 #define FLASH_BASE1_PRELIM      0x0             /* FLASH bank #1        */
 384
 385 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 386 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 387
 388 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 389 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 390
 391 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 392
 393 #define CONFIG_SYS_OR0_PRELIM   0xFF000954              /* Real values for the board */
 394 #define CONFIG_SYS_BR0_PRELIM   0x40000001              /* Real values for the board */
 395
 396 /*
 397  * BR1 and OR1 (SDRAM)
 398  */
 399 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank           */
 400 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 401
 402 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000800      /* BIH is not set       */
 403
 404 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
 405 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 406
 407 /*
 408  * Memory Periodic Timer Prescaler
 409  */
 410
 411 /* periodic timer for refresh */
 412 #define CONFIG_SYS_MAMR_PTA             97      /* start with divider for 100 MHz       */
 413
 414 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 415 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 416 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 417
 418 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 419 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 420 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 421
 422 /*
 423  * MAMR settings for SDRAM
 424  */
 425
 426 /* 8 column SDRAM */
 427 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 428                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 429                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 430 /* 9 column SDRAM */
 431 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 432                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 433                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 434
 435 #define CONFIG_SYS_MAMR         0x13a01114
 436
 437 #ifdef CONFIG_MPC860T
 438
 439 /* Interrupt level assignments.
 440 */
 441 #define FEC_INTERRUPT   SIU_LEVEL1      /* FEC interrupt */
 442
 443 #endif /* CONFIG_MPC860T */
 444
 445
 446 #endif  /* __CONFIG_H */