include/configs/IP860.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  37 #define CONFIG_IP860            1       /* ...on a IP860 board          */
  38 #define CONFIG_BOARD_PRE_INIT   1           /* Call board_pre_init      */
  39
  40 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  41 #define CONFIG_BAUDRATE         9600
  42 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  43
  44 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  45
  46 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
  47 "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"
  48
  49 #undef  CONFIG_BOOTARGS
  50 #define CONFIG_BOOTCOMMAND                                                      \
  51         "bootp; "                                                               \
  52         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  53         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  54         "bootm"
  55
  56 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  57 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  58
  59 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  60
  61
  62 /* enable I2C and select the hardware/software driver */
  63 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  64 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  65 /*
  66  * Software (bit-bang) I2C driver configuration
  67  */
  68 #define PB_SCL          0x00000020      /* PB 26 */
  69 #define PB_SDA          0x00000010      /* PB 27 */
  70
  71 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
  72 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
  73 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  74 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  75 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
  76                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
  77 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
  78                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
  79 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  80
  81
  82 # define CFG_I2C_SPEED          50000
  83 # define CFG_I2C_SLAVE          0xFE
  84 # define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM X24C16                */
  85 # define CFG_I2C_EEPROM_ADDR_LEN 1      /* bytes of address             */
  86 /* mask of address bits that overflow into the "EEPROM chip address"    */
  87 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
  88 #define CFG_EEPROM_PAGE_WRITE_BITS      4
  89 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* takes up to 10 msec */
  90
  91 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
  92                                  CFG_CMD_BEDBUG | \
  93                                  CFG_CMD_I2C    | \
  94                                  CFG_CMD_EEPROM)
  95
  96 #define CONFIG_BOOTP_MASK       CONFIG_BOOTP_DEFAULT
  97
  98 /*----------------------------------------------------------------------*/
  99
 100 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 101 #include <cmd_confdefs.h>
 102
 103 /*----------------------------------------------------------------------*/
 104
 105 /*
 106  * Miscellaneous configurable options
 107  */
 108 #define CFG_LONGHELP                    /* undef to save memory         */
 109 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 110 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 111 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 112 #else
 113 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 114 #endif
 115 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 116 #define CFG_MAXARGS     16              /* max number of command args   */
 117 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 118
 119 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 120 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15MB in DRAM   */
 121
 122 #define CFG_LOAD_ADDR           0x00100000      /* default load address */
 123
 124 #define CFG_PIO_MODE            0       /* IDE interface in PIO Mode 0  */
 125
 126 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 127
 128 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 129
 130 /*
 131  * Low Level Configuration Settings
 132  * (address mappings, register initial values, etc.)
 133  * You should know what you are doing if you make changes here.
 134  */
 135 /*-----------------------------------------------------------------------
 136  * Internal Memory Mapped Register
 137  */
 138 #define CFG_IMMR                0xF1000000      /* Non-standard value!! */
 139
 140 /*-----------------------------------------------------------------------
 141  * Definitions for initial stack pointer and data area (in DPRAM)
 142  */
 143 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 144 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 145 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 146 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 147 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 148
 149 /*-----------------------------------------------------------------------
 150  * Start addresses for the final memory configuration
 151  * (Set up by the startup code)
 152  * Please note that CFG_SDRAM_BASE _must_ start at 0
 153  */
 154 #define CFG_SDRAM_BASE          0x00000000
 155 #define CFG_FLASH_BASE          0x10000000
 156 #ifdef  DEBUG
 157 #define CFG_MONITOR_LEN         (512 << 10)     /* Reserve 512 kB for Monitor   */
 158 #else
 159 #if 0 /* need more space for I2C tests */
 160 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
 161 #else
 162 #define CFG_MONITOR_LEN         (256 << 10)
 163 #endif
 164 #endif
 165 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 166 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 167
 168 /*
 169  * For booting Linux, the board info and command line data
 170  * have to be in the first 8 MB of memory, since this is
 171  * the maximum mapped by the Linux kernel during initialization.
 172  */
 173 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 174 /*-----------------------------------------------------------------------
 175  * FLASH organization
 176  */
 177 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 178 #define CFG_MAX_FLASH_SECT      124     /* max number of sectors on one chip    */
 179
 180 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 181 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 182
 183 #undef  CFG_ENV_IS_IN_FLASH
 184 #undef  CFG_ENV_IS_IN_NVRAM
 185 #undef  CFG_ENV_IS_IN_NVRAM
 186 #undef  DEBUG_I2C
 187 #define CFG_ENV_IS_IN_EEPROM
 188
 189 #ifdef  CFG_ENV_IS_IN_NVRAM
 190 #define CFG_ENV_ADDR            0x20000000      /* use SRAM     */
 191 #define CFG_ENV_SIZE            (16<<10)        /* use 16 kB    */
 192 #endif  /* CFG_ENV_IS_IN_NVRAM */
 193
 194 #ifdef  CFG_ENV_IS_IN_EEPROM
 195 #define CFG_ENV_OFFSET           512    /* Leave 512 bytes free for other data  */
 196 #define CFG_ENV_SIZE            1536    /* Use remaining space                  */
 197 #endif  /* CFG_ENV_IS_IN_EEPROM */
 198
 199 /*-----------------------------------------------------------------------
 200  * Cache Configuration
 201  */
 202 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 203 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 204 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 205 #endif
 206
 207 /*-----------------------------------------------------------------------
 208  * SYPCR - System Protection Control                            11-9
 209  * SYPCR can only be written once after reset!
 210  *-----------------------------------------------------------------------
 211  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 212  * +0x0004
 213  */
 214 #if defined(CONFIG_WATCHDOG)
 215 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 216                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 217 #else
 218 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 219 #endif
 220
 221 /*-----------------------------------------------------------------------
 222  * SIUMCR - SIU Module Configuration                            11-6
 223  *-----------------------------------------------------------------------
 224  * +0x0000 => 0x80600800
 225  */
 226 #define CFG_SIUMCR      (SIUMCR_EARB   | SIUMCR_EARP0 | \
 227                          SIUMCR_DBGC11 | SIUMCR_MLRC10)
 228
 229 /*-----------------------------------------------------------------------
 230  * Clock Setting - get clock frequency from Board Revision Register
 231  *-----------------------------------------------------------------------
 232  */
 233 #ifndef __ASSEMBLY__
 234 extern  unsigned long           ip860_get_clk_freq (void);
 235 #endif
 236 #define CONFIG_8xx_GCLK_FREQ    ip860_get_clk_freq()
 237
 238 /*-----------------------------------------------------------------------
 239  * TBSCR - Time Base Status and Control                         11-26
 240  *-----------------------------------------------------------------------
 241  * Clear Reference Interrupt Status, Timebase freezing enabled
 242  * +0x0200 => 0x00C2
 243  */
 244 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 245
 246 /*-----------------------------------------------------------------------
 247  * PISCR - Periodic Interrupt Status and Control                11-31
 248  *-----------------------------------------------------------------------
 249  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 250  * +0x0240 => 0x0082
 251  */
 252 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 253
 254 /*-----------------------------------------------------------------------
 255  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 256  *-----------------------------------------------------------------------
 257  * Reset PLL lock status sticky bit, timer expired status bit and timer
 258  * interrupt status bit, set PLL multiplication factor !
 259  */
 260 /* +0x0286 => was: 0x0000D000 */
 261 #define CFG_PLPRCR                                                      \
 262                 (       PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 263                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 264                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 265                 )
 266
 267 /*-----------------------------------------------------------------------
 268  * SCCR - System Clock and reset Control Register               15-27
 269  *-----------------------------------------------------------------------
 270  * Set clock output, timebase and RTC source and divider,
 271  * power management and some other internal clocks
 272  */
 273 #define SCCR_MASK       SCCR_EBDF11
 274 #define CFG_SCCR        (SCCR_COM00     |   SCCR_TBS      |     \
 275                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 276                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 277                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 278                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 279                          SCCR_DFNH000)
 280
 281 /*-----------------------------------------------------------------------
 282  * RTCSC - Real-Time Clock Status and Control Register          11-27
 283  *-----------------------------------------------------------------------
 284  */
 285 /* +0x0220 => 0x00C3 */
 286 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 287
 288
 289 /*-----------------------------------------------------------------------
 290  * RCCR - RISC Controller Configuration Register                19-4
 291  *-----------------------------------------------------------------------
 292  */
 293 /* +0x09C4 => TIMEP=1 */
 294 #define CFG_RCCR 0x0100
 295
 296 /*-----------------------------------------------------------------------
 297  * RMDS - RISC Microcode Development Support Control Register
 298  *-----------------------------------------------------------------------
 299  */
 300 #define CFG_RMDS 0
 301
 302 /*-----------------------------------------------------------------------
 303  * DER - Debug Event Register
 304  *-----------------------------------------------------------------------
 305  *
 306  */
 307 #define CFG_DER 0
 308
 309 /*
 310  * Init Memory Controller:
 311  */
 312
 313 /*
 314  * MAMR settings for SDRAM      - 16-14
 315  * => 0xC3804114
 316  */
 317
 318 /* periodic timer for refresh */
 319 #define CFG_MAMR_PTA    0xC3
 320
 321 #define CFG_MAMR        ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 322                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 323                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 324 /*
 325  * BR1 and OR1 (FLASH)
 326  */
 327 #define FLASH_BASE              0x10000000      /* FLASH bank #0        */
 328
 329 /* used to re-map FLASH
 330  * restrict access enough to keep SRAM working (if any)
 331  * but not too much to meddle with FLASH accesses
 332  */
 333 /* allow for max 8 MB of Flash */
 334 #define CFG_REMAP_OR_AM         0xFF800000      /* OR addr mask */
 335 #define CFG_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
 336
 337 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
 338
 339 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 340 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 341 /* 16 bit, bank valid */
 342 #define CFG_BR0_PRELIM  ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 343
 344 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 345 #define CFG_BR1_PRELIM  CFG_BR0_PRELIM
 346
 347 /*
 348  * BR2/OR2 - SDRAM
 349  */
 350 #define SDRAM_BASE              0x00000000      /* SDRAM bank */
 351 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 352 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 353
 354 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 355
 356 #define CFG_OR2         (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 357 #define CFG_BR2         ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 358
 359 /*
 360  * BR3/OR3 - SRAM (16 bit)
 361  */
 362 #define SRAM_BASE       0x20000000
 363 #define CFG_OR3         0xFFF00130              /* BI/SCY = 5/TRLX (internal) */
 364 #define CFG_BR3         ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 365 #define SRAM_SIZE       (1 + (~(CFG_OR3 & BR_BA_MSK)))
 366 #define CFG_OR3_PRELIM  CFG_OR3                 /* Make sure to map early */
 367 #define CFG_BR3_PRELIM  CFG_BR3                 /* in case it's used for ENV */
 368
 369 /*
 370  * BR4/OR4 - Board Control & Status (8 bit)
 371  */
 372 #define BCSR_BASE       0xFC000000
 373 #define CFG_OR4         0xFFFF0120              /* BI (internal) */
 374 #define CFG_BR4         ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 375
 376 /*
 377  * BR5/OR5 - IP Slot A/B (16 bit)
 378  */
 379 #define IP_SLOT_BASE    0x40000000
 380 #define CFG_OR5         0xFE00010C              /* SETA/TRLX/BI/ SCY=0 (external) */
 381 #define CFG_BR5         ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 382
 383 /*
 384  * BR6/OR6 - VME STD  (16 bit)
 385  */
 386 #define VME_STD_BASE    0xFE000000
 387 #define CFG_OR6         0xFF00010C              /* SETA/TRLX/BI/SCY=0  (external) */
 388 #define CFG_BR6         ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 389
 390 /*
 391  * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
 392  */
 393 #define VME_SHORT_BASE  0xFF000000
 394 #define CFG_OR7         0xFF00010C              /* SETA/TRLX/BI/ SCY=0 (external) */
 395 #define CFG_BR7         ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 396
 397 /*-----------------------------------------------------------------------
 398  * Board Control and Status Region:
 399  *-----------------------------------------------------------------------
 400  */
 401 #ifndef __ASSEMBLY__
 402 typedef struct ip860_bcsr_s {
 403         unsigned char   shmem_addr;     /* +00 shared memory address register   */
 404         unsigned char   reserved0;
 405         unsigned char   mbox_addr;      /* +02 mailbox address register         */
 406         unsigned char   reserved1;
 407         unsigned char   vme_int_mask;   /* +04 VME Bus interrupt mask register  */
 408         unsigned char   reserved2;
 409         unsigned char   vme_int_pend;   /* +06 VME interrupt pending register   */
 410         unsigned char   reserved3;
 411         unsigned char   bd_int_mask;    /* +08 board interrupt mask register    */
 412         unsigned char   reserved4;
 413         unsigned char   bd_int_pend;    /* +0A board interrupt pending register */
 414         unsigned char   reserved5;
 415         unsigned char   bd_ctrl;        /* +0C board control register           */
 416         unsigned char   reserved6;
 417         unsigned char   bd_status;      /* +0E board status  register           */
 418         unsigned char   reserved7;
 419         unsigned char   vme_irq;        /* +10 VME interrupt request register   */
 420         unsigned char   reserved8;
 421         unsigned char   vme_ivec;       /* +12 VME interrupt vector register    */
 422         unsigned char   reserved9;
 423         unsigned char   cli_mbox;       /* +14 clear mailbox irq                */
 424         unsigned char   reservedA;
 425         unsigned char   rtc;            /* +16 RTC control register             */
 426         unsigned char   reservedB;
 427         unsigned char   mbox_data;      /* +18 mailbox read/write register      */
 428         unsigned char   reservedC;
 429         unsigned char   wd_trigger;     /* +1A Watchdog trigger register        */
 430         unsigned char   reservedD;
 431         unsigned char   rmw_req;        /* +1C RMW request register             */
 432         unsigned char   reservedE;
 433         unsigned char   bd_rev;         /* +1E Board Revision register          */
 434 } ip860_bcsr_t;
 435 #endif  /* __ASSEMBLY__ */
 436
 437 /*-----------------------------------------------------------------------
 438  * Board Control Register: bd_ctrl (Offset 0x0C)
 439  *-----------------------------------------------------------------------
 440  */
 441 #define BD_CTRL_IPLSE   0x80    /* IP Slot Long Select Enable           */
 442 #define BD_CTRL_WDOGE   0x40    /* Watchdog Enable                      */
 443 #define BD_CTRL_FLWE    0x20    /* Flash Write Enable                   */
 444 #define BD_CTRL_RWDN    0x10    /* VMEBus Requester Release When Done Enable */
 445
 446 /*-----------------------------------------------------------------------
 447  *
 448  *-----------------------------------------------------------------------
 449  *
 450  */
 451
 452 /*
 453  * Internal Definitions
 454  *
 455  * Boot Flags
 456  */
 457 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 458 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 459
 460 #endif  /* __CONFIG_H */