include/configs/IPHASE4539.h

   1 /*
   2  * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
   3  *
   4  * This file is based on similar values for other boards found in
   5  * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*-----------------------------------------------------------------------
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
  39 #define CONFIG_IPHASE4539       1       /* ...on a Interphase 4539 PMC */
  40
  41 #define CONFIG_SYS_TEXT_BASE    0xffb00000
  42
  43 #define CONFIG_CPM2             1       /* Has a CPM2 */
  44
  45 /*-----------------------------------------------------------------------
  46  * select serial console configuration
  47  *
  48  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  49  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  50  * for SCC).
  51  *
  52  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  53  * defined elsewhere (for example, on the cogent platform, there are serial
  54  * ports on the motherboard which are used for the serial console - see
  55  * cogent/cma101/serial.[ch]).
  56  */
  57 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
  58 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
  59 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  60 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  61
  62 /*-----------------------------------------------------------------------
  63  * select ethernet configuration
  64  *
  65  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  66  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  67  * for FCC)
  68  *
  69  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  70  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  71  */
  72 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  73 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  74 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  75 #define CONFIG_ETHER_INDEX      3       /* which channel for ether  */
  76
  77 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
  78
  79 /*-----------------------------------------------------------------------
  80  * - Rx-CLK is CLK14
  81  * - Tx-CLK is CLK16
  82  * - Select bus for bd/buffers (see 28-13)
  83  * - Half duplex
  84  */
  85 # define CONFIG_SYS_CMXFCR_MASK3        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  86 # define CONFIG_SYS_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
  87 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  88 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  89
  90 #endif  /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  91
  92 /* other options */
  93
  94 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
  95 #define CONFIG_BAUDRATE         19200
  96
  97 /*
  98  * BOOTP options
  99  */
 100 #define CONFIG_BOOTP_SUBNETMASK
 101 #define CONFIG_BOOTP_GATEWAY
 102 #define CONFIG_BOOTP_HOSTNAME
 103 #define CONFIG_BOOTP_BOOTPATH
 104 #define CONFIG_BOOTP_BOOTFILESIZE
 105
 106 /*
 107  * select i2c support configuration
 108  *
 109  * Supported configurations are {none, software, hardware} drivers.
 110  * If the software driver is chosen, there are some additional
 111  * configuration items that the driver uses to drive the port pins.
 112  */
 113 #define CONFIG_SYS_I2C
 114 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 115 #define CONFIG_SYS_I2C_SOFT_SPEED       400000
 116 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 117 /*
 118  * Software (bit-bang) I2C driver configuration
 119  */
 120 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 121 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 122 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 123 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 124 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 125                         else    iop->pdat &= ~0x00010000
 126 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 127                         else    iop->pdat &= ~0x00020000
 128 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 129
 130
 131 /*
 132  * Command line configuration.
 133  */
 134 #include <config_cmd_default.h>
 135
 136
 137 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 138 #define CONFIG_BOOTCOMMAND      "bootm 100000"  /* autoboot command */
 139 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 140
 141 #if defined(CONFIG_CMD_KGDB)
 142 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 143 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 144 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 145 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 146 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 147 #endif
 148
 149 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 150
 151 /*-----------------------------------------------------------------------
 152  * Miscellaneous configurable options
 153  */
 154 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 155 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 156 #if defined(CONFIG_CMD_KGDB)
 157 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 158 #else
 159 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 160 #endif
 161 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
 162 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 163 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 164
 165 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 166 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15 MB in DRAM  */
 167
 168 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passed to Linux in MHz */
 169                                         /* for versions < 2.4.5-pre5     */
 170
 171 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 172
 173 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 174
 175 #define CONFIG_SYS_RESET_ADDRESS        0x04400000
 176
 177 #define CONFIG_MISC_INIT_R      1       /* We need misc_init_r()        */
 178
 179 /*-----------------------------------------------------------------------
 180  * For booting Linux, the board info and command line data
 181  * have to be in the first 8 MB of memory, since this is
 182  * the maximum mapped by the Linux kernel during initialization.
 183  */
 184 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 185
 186 /*-----------------------------------------------------------------------
 187  * Start addresses for the final memory configuration (Setup by the
 188  * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
 189  */
 190 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 191 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 192
 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 194 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor  */
 195 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 196
 197 /*-----------------------------------------------------------------------
 198  * FLASH organization
 199  */
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 201 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max num of sects on one chip */
 202 #define CONFIG_SYS_MAX_FLASH_SIZE       (CONFIG_SYS_MAX_FLASH_SECT * 0x10000)   /* 4 MB */
 203
 204 #define CONFIG_SYS_FLASH_ERASE_TOUT     2400000 /* Flash Erase Timeout (in ms)  */
 205 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 206
 207 /* Environment in FLASH, there is little space left in Serial EEPROM */
 208 #define CONFIG_ENV_IS_IN_FLASH  1
 209 #define CONFIG_ENV_SECT_SIZE    0x10000 /* We use one complete sector   */
 210 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
 211
 212
 213 /*-----------------------------------------------------------------------
 214  * Hard Reset Configuration Words
 215  *
 216  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 217  * defines for the various registers affected by the HRCW e.g. changing
 218  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 219  */
 220 #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )              |\
 221                           ( HRCW_L2CPC10 | HRCW_ISB110 )        |\
 222                           ( HRCW_MMR11 | HRCW_APPC10 )          |\
 223                           ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )   \
 224                         ) /* 0x14863245 */
 225
 226 /* no slaves */
 227 #define CONFIG_SYS_HRCW_SLAVE1 0
 228 #define CONFIG_SYS_HRCW_SLAVE2 0
 229 #define CONFIG_SYS_HRCW_SLAVE3 0
 230 #define CONFIG_SYS_HRCW_SLAVE4 0
 231 #define CONFIG_SYS_HRCW_SLAVE5 0
 232 #define CONFIG_SYS_HRCW_SLAVE6 0
 233 #define CONFIG_SYS_HRCW_SLAVE7 0
 234
 235 /*-----------------------------------------------------------------------
 236  * Internal Memory Mapped Register
 237  */
 238 #define CONFIG_SYS_IMMR         0xFF000000 /* We keep original value */
 239
 240 /*-----------------------------------------------------------------------
 241  * Definitions for initial stack pointer and data area (in DPRAM)
 242  */
 243 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 244 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 245 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 246 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 247
 248 /*-----------------------------------------------------------------------
 249  * Cache Configuration
 250  */
 251 #define CONFIG_SYS_CACHELINE_SIZE       32     /* For MPC8260 CPU               */
 252 #if defined(CONFIG_CMD_KGDB)
 253 # define CONFIG_SYS_CACHELINE_SHIFT     5      /* log base 2 of the above value */
 254 #endif
 255
 256 /*-----------------------------------------------------------------------
 257  * HIDx - Hardware Implementation-dependent Registers           2-11
 258  *-----------------------------------------------------------------------
 259  * HID0 also contains cache control.
 260  *
 261  * HID1 has only read-only information - nothing to set.
 262  */
 263 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 264                          HID0_IFEM|HID0_ABE)
 265 #define CONFIG_SYS_HID0_FINAL   (HID0_IFEM|HID0_ABE)
 266 #define CONFIG_SYS_HID2 0
 267
 268 /*-----------------------------------------------------------------------
 269  * RMR - Reset Mode Register                                     5-5
 270  *-----------------------------------------------------------------------
 271  * turn on Checkstop Reset Enable
 272  */
 273 #define CONFIG_SYS_RMR          RMR_CSRE
 274
 275 /*-----------------------------------------------------------------------
 276  * BCR - Bus Configuration                                       4-25
 277  *-----------------------------------------------------------------------
 278  */
 279 #define CONFIG_SYS_BCR          0xA01C0000
 280
 281 /*-----------------------------------------------------------------------
 282  * SIUMCR - SIU Module Configuration                             4-31
 283  *-----------------------------------------------------------------------
 284  */
 285 #define CONFIG_SYS_SIUMCR       0X4205C000
 286
 287 /*-----------------------------------------------------------------------
 288  * SYPCR - System Protection Control                             4-35
 289  * SYPCR can only be written once after reset!
 290  *-----------------------------------------------------------------------
 291  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 292  */
 293 #if defined (CONFIG_WATCHDOG)
 294 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 295                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 296 #else
 297 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 298                          SYPCR_SWRI|SYPCR_SWP)
 299 #endif /* CONFIG_WATCHDOG */
 300
 301 /*-----------------------------------------------------------------------
 302  * TMCNTSC - Time Counter Status and Control                     4-40
 303  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 304  * and enable Time Counter
 305  *-----------------------------------------------------------------------
 306  */
 307 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 308
 309 /*-----------------------------------------------------------------------
 310  * PISCR - Periodic Interrupt Status and Control                 4-42
 311  *-----------------------------------------------------------------------
 312  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 313  * Periodic timer
 314  */
 315 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 316
 317 /*-----------------------------------------------------------------------
 318  * SCCR - System Clock Control                                   9-8
 319  *-----------------------------------------------------------------------
 320  * Ensure DFBRG is Divide by 16
 321  */
 322 #define CONFIG_SYS_SCCR 0
 323
 324 /*-----------------------------------------------------------------------
 325  * RCCR - RISC Controller Configuration                         13-7
 326  *-----------------------------------------------------------------------
 327  */
 328 #define CONFIG_SYS_RCCR 0
 329
 330 /*-----------------------------------------------------------------------
 331  * Init Memory Controller:
 332  *
 333  * Bank Bus     Machine PortSz  Device
 334  * ---- ---     ------- ------  ------
 335  *  0   60x     GPCM    64 bit  FLASH
 336  *  1   60x     SDRAM   64 bit  SDRAM
 337  */
 338
 339 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
 340 #define CONFIG_SYS_OR0_PRELIM   0xFF800882
 341 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
 342 #define CONFIG_SYS_OR1_PRELIM   0xF8002CD0
 343
 344 #define CONFIG_SYS_PSDMR        0x404A241A
 345 #define CONFIG_SYS_MPTPR        0x00007400
 346 #define CONFIG_SYS_PSRT 0x00000007
 347
 348 #endif /* __CONFIG_H */