include/configs/IPHASE4539.h

   1 /*
   2  * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
   3  *
   4  * This file is based on similar values for other boards found in
   5  * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #undef DEBUG                            /* General debug */
  34
  35 /*-----------------------------------------------------------------------
  36  * High Level Configuration Options
  37  * (easy to change)
  38  */
  39
  40 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
  41 #define CONFIG_IPHASE4539       1       /* ...on a Interphase 4539 PMC */
  42
  43 #define CONFIG_CPM2             1       /* Has a CPM2 */
  44
  45 /*-----------------------------------------------------------------------
  46  * select serial console configuration
  47  *
  48  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  49  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  50  * for SCC).
  51  *
  52  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  53  * defined elsewhere (for example, on the cogent platform, there are serial
  54  * ports on the motherboard which are used for the serial console - see
  55  * cogent/cma101/serial.[ch]).
  56  */
  57 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
  58 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
  59 #undef  CONFIG_CONS_NONE                /* define if console on something else */
  60 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  61
  62 /*-----------------------------------------------------------------------
  63  * select ethernet configuration
  64  *
  65  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  66  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  67  * for FCC)
  68  *
  69  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  70  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  71  */
  72 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC   */
  73 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC   */
  74 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  75 #define CONFIG_ETHER_INDEX      3       /* which channel for ether  */
  76
  77 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
  78
  79 /*-----------------------------------------------------------------------
  80  * - Rx-CLK is CLK14
  81  * - Tx-CLK is CLK16
  82  * - Select bus for bd/buffers (see 28-13)
  83  * - Half duplex
  84  */
  85 # define CFG_CMXFCR_MASK        (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  86 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
  87 # define CFG_CPMFCR_RAMTYPE     0
  88 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
  89
  90 #endif  /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  91
  92 /* other options */
  93
  94 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
  95 #define CONFIG_BAUDRATE         19200
  96
  97 /*
  98  * BOOTP options
  99  */
 100 #define CONFIG_BOOTP_SUBNETMASK
 101 #define CONFIG_BOOTP_GATEWAY
 102 #define CONFIG_BOOTP_HOSTNAME
 103 #define CONFIG_BOOTP_BOOTPATH
 104 #define CONFIG_BOOTP_BOOTFILESIZE
 105
 106 /*
 107  * select i2c support configuration
 108  *
 109  * Supported configurations are {none, software, hardware} drivers.
 110  * If the software driver is chosen, there are some additional
 111  * configuration items that the driver uses to drive the port pins.
 112  */
 113 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 114 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 115 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 116 #define CFG_I2C_SLAVE           0x7F
 117
 118 /*
 119  * Software (bit-bang) I2C driver configuration
 120  */
 121 #ifdef CONFIG_SOFT_I2C
 122 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 123 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 124 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 125 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 126 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 127                         else    iop->pdat &= ~0x00010000
 128 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 129                         else    iop->pdat &= ~0x00020000
 130 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 131 #endif /* CONFIG_SOFT_I2C */
 132
 133
 134 /*
 135  * Command line configuration.
 136  */
 137 #include <config_cmd_default.h>
 138
 139
 140 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 141 #define CONFIG_BOOTCOMMAND      "bootm 100000"  /* autoboot command */
 142 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 143
 144 #if defined(CONFIG_CMD_KGDB)
 145 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 146 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 147 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 148 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 149 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 150 #endif
 151
 152 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 153
 154 /*-----------------------------------------------------------------------
 155  * Miscellaneous configurable options
 156  */
 157 #define CFG_LONGHELP                    /* undef to save memory         */
 158 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 159 #if defined(CONFIG_CMD_KGDB)
 160 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 161 #else
 162 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 163 #endif
 164 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
 165 #define CFG_MAXARGS     16              /* max number of command args   */
 166 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 167
 168 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 169 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15 MB in DRAM  */
 170
 171 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passed to Linux in MHz */
 172                                         /* for versions < 2.4.5-pre5     */
 173
 174 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 175
 176 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 177
 178 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 179
 180 #define CFG_RESET_ADDRESS       0x04400000
 181
 182 #define CONFIG_MISC_INIT_R      1       /* We need misc_init_r()        */
 183
 184 /*-----------------------------------------------------------------------
 185  * For booting Linux, the board info and command line data
 186  * have to be in the first 8 MB of memory, since this is
 187  * the maximum mapped by the Linux kernel during initialization.
 188  */
 189 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 190
 191 /*-----------------------------------------------------------------------
 192  * Start addresses for the final memory configuration (Setup by the
 193  * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
 194  */
 195 #define CFG_SDRAM_BASE          0x00000000
 196 #define CFG_FLASH_BASE          0xFF800000
 197
 198 #define CFG_MONITOR_BASE        TEXT_BASE
 199 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor  */
 200 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc() */
 201
 202 /*-----------------------------------------------------------------------
 203  * FLASH organization
 204  */
 205 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 206 #define CFG_MAX_FLASH_SECT      64      /* max num of sects on one chip */
 207 #define CFG_MAX_FLASH_SIZE      (CFG_MAX_FLASH_SECT * 0x10000)  /* 4 MB */
 208
 209 #define CFG_FLASH_ERASE_TOUT    2400000 /* Flash Erase Timeout (in ms)  */
 210 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 211
 212 /* Environment in FLASH, there is little space left in Serial EEPROM */
 213 #define CFG_ENV_IS_IN_FLASH     1
 214 #define CFG_ENV_SECT_SIZE       0x10000 /* We use one complete sector   */
 215 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x10000) /* 2. sector */
 216
 217
 218 /*-----------------------------------------------------------------------
 219  * Hard Reset Configuration Words
 220  *
 221  * if you change bits in the HRCW, you must also change the CFG_*
 222  * defines for the various registers affected by the HRCW e.g. changing
 223  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 224  */
 225 #define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )             |\
 226                           ( HRCW_L2CPC10 | HRCW_ISB110 )        |\
 227                           ( HRCW_MMR11 | HRCW_APPC10 )          |\
 228                           ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )   \
 229                         ) /* 0x14863245 */
 230
 231 /* no slaves */
 232 #define CFG_HRCW_SLAVE1 0
 233 #define CFG_HRCW_SLAVE2 0
 234 #define CFG_HRCW_SLAVE3 0
 235 #define CFG_HRCW_SLAVE4 0
 236 #define CFG_HRCW_SLAVE5 0
 237 #define CFG_HRCW_SLAVE6 0
 238 #define CFG_HRCW_SLAVE7 0
 239
 240 /*-----------------------------------------------------------------------
 241  * Internal Memory Mapped Register
 242  */
 243 #define CFG_IMMR                0xFF000000 /* We keep original value */
 244
 245 /*-----------------------------------------------------------------------
 246  * Definitions for initial stack pointer and data area (in DPRAM)
 247  */
 248 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 249 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 250 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 251 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 252 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 253
 254 /*-----------------------------------------------------------------------
 255  * Internal Definitions
 256  *
 257  * Boot Flags
 258  */
 259 #define BOOTFLAG_COLD   0x01      /* Normal Power-On: Boot from FLASH   */
 260 #define BOOTFLAG_WARM   0x02      /* Software reboot                    */
 261
 262
 263 /*-----------------------------------------------------------------------
 264  * Cache Configuration
 265  */
 266 #define CFG_CACHELINE_SIZE      32     /* For MPC8260 CPU               */
 267 #if defined(CONFIG_CMD_KGDB)
 268 # define CFG_CACHELINE_SHIFT    5      /* log base 2 of the above value */
 269 #endif
 270
 271 /*-----------------------------------------------------------------------
 272  * HIDx - Hardware Implementation-dependent Registers           2-11
 273  *-----------------------------------------------------------------------
 274  * HID0 also contains cache control.
 275  *
 276  * HID1 has only read-only information - nothing to set.
 277  */
 278 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 279                          HID0_IFEM|HID0_ABE)
 280 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 281 #define CFG_HID2        0
 282
 283 /*-----------------------------------------------------------------------
 284  * RMR - Reset Mode Register                                     5-5
 285  *-----------------------------------------------------------------------
 286  * turn on Checkstop Reset Enable
 287  */
 288 #define CFG_RMR         RMR_CSRE
 289
 290 /*-----------------------------------------------------------------------
 291  * BCR - Bus Configuration                                       4-25
 292  *-----------------------------------------------------------------------
 293  */
 294 #define CFG_BCR         0xA01C0000
 295
 296 /*-----------------------------------------------------------------------
 297  * SIUMCR - SIU Module Configuration                             4-31
 298  *-----------------------------------------------------------------------
 299  */
 300 #define CFG_SIUMCR      0X4205C000
 301
 302 /*-----------------------------------------------------------------------
 303  * SYPCR - System Protection Control                             4-35
 304  * SYPCR can only be written once after reset!
 305  *-----------------------------------------------------------------------
 306  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 307  */
 308 #if defined (CONFIG_WATCHDOG)
 309 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 310                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 311 #else
 312 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 313                          SYPCR_SWRI|SYPCR_SWP)
 314 #endif /* CONFIG_WATCHDOG */
 315
 316 /*-----------------------------------------------------------------------
 317  * TMCNTSC - Time Counter Status and Control                     4-40
 318  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 319  * and enable Time Counter
 320  *-----------------------------------------------------------------------
 321  */
 322 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 323
 324 /*-----------------------------------------------------------------------
 325  * PISCR - Periodic Interrupt Status and Control                 4-42
 326  *-----------------------------------------------------------------------
 327  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 328  * Periodic timer
 329  */
 330 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 331
 332 /*-----------------------------------------------------------------------
 333  * SCCR - System Clock Control                                   9-8
 334  *-----------------------------------------------------------------------
 335  * Ensure DFBRG is Divide by 16
 336  */
 337 #define CFG_SCCR        0
 338
 339 /*-----------------------------------------------------------------------
 340  * RCCR - RISC Controller Configuration                         13-7
 341  *-----------------------------------------------------------------------
 342  */
 343 #define CFG_RCCR        0
 344
 345 /*-----------------------------------------------------------------------
 346  * Init Memory Controller:
 347  *
 348  * Bank Bus     Machine PortSz  Device
 349  * ---- ---     ------- ------  ------
 350  *  0   60x     GPCM    64 bit  FLASH
 351  *  1   60x     SDRAM   64 bit  SDRAM
 352  */
 353
 354 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
 355 #define CFG_OR0_PRELIM  0xFF800882
 356 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
 357 #define CFG_OR1_PRELIM  0xF8002CD0
 358
 359 #define CFG_PSDMR       0x404A241A
 360 #define CFG_MPTPR       0x00007400
 361 #define CFG_PSRT        0x00000007
 362
 363 #endif /* __CONFIG_H */