include/configs/ISPAN.h

   1 /*
   2  * Copyright (C) 2004 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Support for Interphase iSPAN Communications Controllers
   6  * (453x and others). Tested on 4532.
   7  *
   8  * Derived from iSPAN 4539 port (iphase4539) by
   9  * Wolfgang Grandegger <wg@denx.de>
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 #define CONFIG_MPC8260                  /* This is an MPC8260 CPU               */
  33 #define CONFIG_ISPAN                    /* ...on one of Interphase iSPAN boards */
  34
  35 /*-----------------------------------------------------------------------
  36  * Select serial console configuration
  37  *
  38  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  39  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  40  * for SCC).
  41  *
  42  * If CONFIG_CONS_NONE is defined, then the serial console routines must be
  43  * defined elsewhere (for example, on the cogent platform, there are serial
  44  * ports on the motherboard which are used for the serial console - see
  45  * cogent/cma101/serial.[ch]).
  46  */
  47 #define CONFIG_CONS_ON_SMC              /* Define if console on SMC             */
  48 #undef  CONFIG_CONS_ON_SCC              /* Define if console on SCC             */
  49 #undef  CONFIG_CONS_NONE                /* Define if console on something else  */
  50 #define CONFIG_CONS_INDEX       1       /* Which serial channel for console     */
  51
  52 /*-----------------------------------------------------------------------
  53  * Select Ethernet configuration
  54  *
  55  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  56  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  57  * for FCC).
  58  *
  59  * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
  60  * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  61  * from CONFIG_COMMANDS to remove support for networking.
  62  */
  63 #undef  CONFIG_ETHER_ON_SCC             /* Define if Ethernet on SCC            */
  64 #define CONFIG_ETHER_ON_FCC             /* Define if Ethernet on FCC            */
  65 #undef  CONFIG_ETHER_NONE               /* Define if Ethernet on something else */
  66 #define CONFIG_ETHER_INDEX      3       /* Which channel for Ethernrt           */
  67
  68 #ifdef CONFIG_ETHER_ON_FCC
  69
  70 #if CONFIG_ETHER_INDEX == 3
  71
  72 #define CFG_PHY_ADDR            0
  73 #define CFG_CMXFCR_VALUE        (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
  74 #define CFG_CMXFCR_MASK         (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
  75
  76 #endif /* CONFIG_ETHER_INDEX == 3 */
  77
  78 #define CFG_CPMFCR_RAMTYPE      0
  79 #define CFG_FCC_PSMR            (FCC_PSMR_FDE | FCC_PSMR_LPB)
  80
  81 #define CONFIG_MII                              /* MII PHY management           */
  82 #define CONFIG_BITBANGMII                       /* Bit-bang MII PHY management  */
  83 /*
  84  * GPIO pins used for bit-banged MII communications
  85  */
  86 #define MDIO_PORT               3               /* Port D */
  87
  88 #define CFG_MDIO_PIN            0x00040000      /* PD13 */
  89 #define CFG_MDC_PIN             0x00080000      /* PD12 */
  90
  91 #define MDIO_ACTIVE             (iop->pdir |=  CFG_MDIO_PIN)
  92 #define MDIO_TRISTATE           (iop->pdir &= ~CFG_MDIO_PIN)
  93 #define MDIO_READ               ((iop->pdat &  CFG_MDIO_PIN) != 0)
  94
  95 #define MDIO(bit)               if(bit) iop->pdat |=  CFG_MDIO_PIN; \
  96                                 else    iop->pdat &= ~CFG_MDIO_PIN
  97
  98 #define MDC(bit)                if(bit) iop->pdat |=  CFG_MDC_PIN; \
  99                                 else    iop->pdat &= ~CFG_MDC_PIN
 100
 101 #define MIIDELAY                udelay(1)
 102
 103 #endif /* CONFIG_ETHER_ON_FCC */
 104
 105 #define CONFIG_8260_CLKIN       65536000        /* in Hz */
 106 #define CONFIG_BAUDRATE         38400
 107
 108 #define CONFIG_COMMANDS         ( CONFIG_CMD_DFL  \
 109                                 | CFG_CMD_ASKENV  \
 110                                 | CFG_CMD_DHCP    \
 111                                 | CFG_CMD_ECHO    \
 112                                 | CFG_CMD_IMMAP   \
 113                                 | CFG_CMD_MII     \
 114                                 | CFG_CMD_PING    \
 115                                 | CFG_CMD_REGINFO \
 116                                 )
 117
 118 /* This must be included AFTER the definition of CONFIG_COMMANDS */
 119 #include <cmd_confdefs.h>
 120
 121 #define CONFIG_BOOTDELAY        5               /* autoboot after 5 seconds     */
 122 #define CONFIG_BOOTCOMMAND      "bootm fe010000"        /* autoboot command     */
 123 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
 124
 125 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
 126 #undef  CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
 127
 128 /*-----------------------------------------------------------------------
 129  * Miscellaneous configurable options
 130  */
 131 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt       */
 132 #define CFG_HUSH_PARSER
 133 #define CFG_PROMPT_HUSH_PS2     "> "
 134 #define CFG_LONGHELP                            /* #undef to save memory        */
 135 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 136 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)  /* Print Buffer Size */
 137 #define CFG_MAXARGS             16              /* Max number of command args   */
 138 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 139
 140 #define CFG_MEMTEST_START       0x00100000      /* memtest works on             */
 141 #define CFG_MEMTEST_END         0x03B00000      /* 1 ... 59 MB in SDRAM         */
 142
 143 #define CFG_LOAD_ADDR           0x100000        /* Default load address         */
 144
 145 #define CFG_HZ                  1000            /* Decrementer freq: 1 ms ticks */
 146
 147 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 148
 149 #define CFG_RESET_ADDRESS       0x09900000
 150
 151 #define CONFIG_MISC_INIT_R                      /* We need misc_init_r()        */
 152
 153 /*-----------------------------------------------------------------------
 154  * For booting Linux, the board info and command line data
 155  * have to be in the first 8 MB of memory, since this is
 156  * the maximum mapped by the Linux kernel during initialization.
 157  */
 158 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 159
 160 #define CFG_MONITOR_BASE        TEXT_BASE
 161 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 162 #ifdef CONFIG_BZIP2
 163 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 164 #else
 165 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 KB for malloc()  */
 166 #endif /* CONFIG_BZIP2 */
 167
 168 /*-----------------------------------------------------------------------
 169  * FLASH organization
 170  */
 171 #define CFG_FLASH_BASE          0xFE000000
 172 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 173 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 174 #define CFG_MAX_FLASH_BANKS     1               /* Max num of memory banks      */
 175 #define CFG_MAX_FLASH_SECT      142             /* Max num of sects on one chip */
 176
 177 /* Environment is in flash, there is little space left in Serial EEPROM */
 178 #define CFG_ENV_IS_IN_FLASH
 179 #define CFG_ENV_SECT_SIZE       0x10000         /* We use one complete sector   */
 180 #define CFG_ENV_SIZE            (CFG_ENV_SECT_SIZE)
 181 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 182 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 183 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 184
 185 /*-----------------------------------------------------------------------
 186  * Hard Reset Configuration Words
 187  *
 188  * If you change bits in the HRCW, you must also change the CFG_*
 189  * defines for the various registers affected by the HRCW e.g. changing
 190  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 191  */
 192 /* 0x1686B245 */
 193 #define CFG_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
 194                          HRCW_L2CPC10  | HRCW_ISB110                    |\
 195                          HRCW_BMS      | HRCW_MMR11       | HRCW_APPC10 |\
 196                          HRCW_CS10PC01 | HRCW_MODCK_H0101                \
 197                         )
 198 /* No slaves */
 199 #define CFG_HRCW_SLAVE1 0
 200 #define CFG_HRCW_SLAVE2 0
 201 #define CFG_HRCW_SLAVE3 0
 202 #define CFG_HRCW_SLAVE4 0
 203 #define CFG_HRCW_SLAVE5 0
 204 #define CFG_HRCW_SLAVE6 0
 205 #define CFG_HRCW_SLAVE7 0
 206
 207 /*-----------------------------------------------------------------------
 208  * Internal Memory Mapped Register
 209  */
 210 #define CFG_IMMR                0xF0F00000
 211 #ifdef CFG_REV_B
 212 #define CFG_DEFAULT_IMMR        0xFF000000
 213 #endif /* CFG_REV_B */
 214 /*-----------------------------------------------------------------------
 215  * Definitions for initial stack pointer and data area (in DPRAM)
 216  */
 217 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 218 #define CFG_INIT_RAM_END        0x4000          /* End of used area in DPRAM    */
 219 #define CFG_GBL_DATA_SIZE       128  /* Size in bytes reserved for initial data */
 220 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 221 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 222
 223 /*-----------------------------------------------------------------------
 224  * Internal Definitions
 225  *
 226  * Boot Flags
 227  */
 228 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from flash     */
 229 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 230
 231 /*-----------------------------------------------------------------------
 232  * Cache Configuration
 233  */
 234 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU                      */
 235
 236 /*-----------------------------------------------------------------------
 237  * HIDx - Hardware Implementation-dependent Registers           2-11
 238  *-----------------------------------------------------------------------
 239  * HID0 also contains cache control.
 240  *
 241  * HID1 has only read-only information - nothing to set.
 242  */
 243 #define CFG_HID0_INIT           (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 244                                 HID0_IFEM|HID0_ABE)
 245 #define CFG_HID0_FINAL          (HID0_ICE|HID0_IFEM|HID0_ABE)
 246 #define CFG_HID2                0
 247
 248 /*-----------------------------------------------------------------------
 249  * RMR - Reset Mode Register                                     5-5
 250  *-----------------------------------------------------------------------
 251  * turn on Checkstop Reset Enable
 252  */
 253 #define CFG_RMR                 RMR_CSRE
 254
 255 /*-----------------------------------------------------------------------
 256  * BCR - Bus Configuration                                       4-25
 257  *-----------------------------------------------------------------------
 258  */
 259 #define CFG_BCR                 0xA01C0000
 260
 261 /*-----------------------------------------------------------------------
 262  * SIUMCR - SIU Module Configuration                             4-31
 263  *-----------------------------------------------------------------------
 264  */
 265 #define CFG_SIUMCR              0x42250000/* 0x4205C000 */
 266
 267 /*-----------------------------------------------------------------------
 268  * SYPCR - System Protection Control                             4-35
 269  * SYPCR can only be written once after reset!
 270  *-----------------------------------------------------------------------
 271  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 272  */
 273 #if defined (CONFIG_WATCHDOG)
 274 #define CFG_SYPCR               (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 275                                 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 276 #else
 277 #define CFG_SYPCR               (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 278                                 SYPCR_SWRI|SYPCR_SWP)
 279 #endif /* CONFIG_WATCHDOG */
 280
 281 /*-----------------------------------------------------------------------
 282  * TMCNTSC - Time Counter Status and Control                     4-40
 283  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 284  * and enable Time Counter
 285  *-----------------------------------------------------------------------
 286  */
 287 #define CFG_TMCNTSC             (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 288
 289 /*-----------------------------------------------------------------------
 290  * PISCR - Periodic Interrupt Status and Control                 4-42
 291  *-----------------------------------------------------------------------
 292  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 293  * Periodic timer
 294  */
 295 #define CFG_PISCR               (PISCR_PS|PISCR_PTF|PISCR_PTE)
 296
 297 /*-----------------------------------------------------------------------
 298  * SCCR - System Clock Control                                   9-8
 299  *-----------------------------------------------------------------------
 300  * Ensure DFBRG is Divide by 16
 301  */
 302 #define CFG_SCCR                SCCR_DFBRG01
 303
 304 /*-----------------------------------------------------------------------
 305  * RCCR - RISC Controller Configuration                         13-7
 306  *-----------------------------------------------------------------------
 307  */
 308 #define CFG_RCCR                0
 309
 310 /*-----------------------------------------------------------------------
 311  * Init Memory Controller:
 312  *
 313  * Bank Bus     Machine PortSize                        Device
 314  * ---- ---     ------- -----------------------------   ------
 315  *  0   60x     GPCM     8 bit (Rev.B)/16 bit (Rev.D)   Flash
 316  *  1   60x     SDRAM   64 bit                          SDRAM
 317  *  2   Local   SDRAM   32 bit                          SDRAM
 318  */
 319 #define CFG_USE_FIRMWARE        /* If defined - do not initialise memory
 320                                    controller, rely on initialisation
 321                                    performed by the Interphase boot firmware.
 322                                  */
 323
 324 #define CFG_OR0_PRELIM          0xFE000882
 325 #ifdef CFG_REV_B
 326 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | BRx_PS_8  | BRx_V)
 327 #else  /* Rev. D */
 328 #define CFG_BR0_PRELIM          (CFG_FLASH_BASE | BRx_PS_16 | BRx_V)
 329 #endif /* CFG_REV_B */
 330
 331 #define CFG_MPTPR               0x7F00
 332
 333 /* Please note that 60x SDRAM MUST start at 0 */
 334 #define CFG_SDRAM_BASE          0x00000000
 335 #define CFG_60x_BR              0x00000041
 336 #define CFG_60x_OR              0xF0002CD0
 337 #define CFG_PSDMR               0x0049929A
 338 #define CFG_PSRT                0x07
 339
 340 #define CFG_LSDRAM_BASE         0xF7000000
 341 #define CFG_LOC_BR              0x00001861
 342 #define CFG_LOC_OR              0xFF803280
 343 #define CFG_LSDMR               0x8285A552
 344 #define CFG_LSRT                0x07
 345
 346 #endif /* __CONFIG_H */