include/configs/IVMS8.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  21 #define CONFIG_IVMS8            1       /* ...on a IVMS8 board          */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  24
  25 #if defined (CONFIG_IVMS8_16M)
  26 # define CONFIG_IDENT_STRING     " IVMS8"
  27 #elif defined (CONFIG_IVMS8_32M)
  28 # define CONFIG_IDENT_STRING     " IVMS8_128"
  29 #elif defined (CONFIG_IVMS8_64M)
  30 # define CONFIG_IDENT_STRING     " IVMS8_256"
  31 #endif
  32
  33 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  34 #undef  CONFIG_8xx_CONS_SMC2
  35 #undef  CONFIG_8xx_CONS_NONE
  36 #define CONFIG_BAUDRATE         115200
  37
  38 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  39
  40 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  41 #define CONFIG_8xx_GCLK_FREQ    50331648
  42
  43 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* Show boot progress on LEDs   */
  44
  45 #if 0
  46 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  47 #else
  48 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  49 #endif
  50 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  51
  52 #define CONFIG_BOOTARGS         "root=/dev/nfs rw "                     \
  53                                 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "   \
  54                                 "nfsaddrs=10.0.0.99:10.0.0.2"
  55
  56 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  57 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  58
  59 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  60
  61 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #include <config_cmd_default.h>
  67
  68 #define CONFIG_CMD_IDE
  69
  70
  71 #define CONFIG_MAC_PARTITION
  72 #define CONFIG_DOS_PARTITION
  73
  74 /*
  75  * BOOTP options
  76  */
  77 #define CONFIG_BOOTP_SUBNETMASK
  78 #define CONFIG_BOOTP_HOSTNAME
  79 #define CONFIG_BOOTP_BOOTPATH
  80 #define CONFIG_BOOTP_BOOTFILESIZE
  81
  82
  83 /*
  84  * Miscellaneous configurable options
  85  */
  86 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  87 #if defined(CONFIG_CMD_KGDB)
  88 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  89 #else
  90 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  91 #endif
  92 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  93 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  94 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  95
  96 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
  97 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
  98
  99 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 100
 101 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 102
 103 #define CONFIG_SYS_PB_SDRAM_CLKE        0x00008000              /* PB 16        */
 104 #define CONFIG_SYS_PB_ETH_POWERDOWN     0x00010000              /* PB 15        */
 105 #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000              /* PB 14        */
 106
 107 #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010)        /* PC 11        */
 108 #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020)        /* PC 10        */
 109
 110 /*
 111  * Low Level Configuration Settings
 112  * (address mappings, register initial values, etc.)
 113  * You should know what you are doing if you make changes here.
 114  */
 115 /*-----------------------------------------------------------------------
 116  * Internal Memory Mapped Register
 117  */
 118 #define CONFIG_SYS_IMMR         0xFFF00000 /* was: 0xFF000000 */
 119
 120 /*-----------------------------------------------------------------------
 121  * Definitions for initial stack pointer and data area (in DPRAM)
 122  */
 123 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 124 #if defined (CONFIG_IVMS8_16M)
 125 # define        CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 126 #elif defined (CONFIG_IVMS8_32M)
 127 # define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 128 #elif defined (CONFIG_IVMS8_64M)
 129 # define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 130 #endif
 131
 132 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 133 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 134
 135 /*-----------------------------------------------------------------------
 136  * Start addresses for the final memory configuration
 137  * (Set up by the startup code)
 138  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 139  */
 140 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 141 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 142 #ifdef  DEBUG
 143 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 144 #else
 145 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 146 #endif
 147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 148 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 149
 150 /*
 151  * For booting Linux, the board info and command line data
 152  * have to be in the first 8 MB of memory, since this is
 153  * the maximum mapped by the Linux kernel during initialization.
 154  */
 155 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 156 /*-----------------------------------------------------------------------
 157  * FLASH organization
 158  */
 159 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 160 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 161
 162 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 163 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 164
 165 #define CONFIG_ENV_IS_IN_FLASH  1
 166 #define CONFIG_ENV_OFFSET               0x7A000 /*   Offset   of Environment Sector     */
 167 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 168 /*-----------------------------------------------------------------------
 169  * Cache Configuration
 170  */
 171 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 172 #if defined(CONFIG_CMD_KGDB)
 173 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 174 #endif
 175
 176 /*-----------------------------------------------------------------------
 177  * SYPCR - System Protection Control                            11-9
 178  * SYPCR can only be written once after reset!
 179  *-----------------------------------------------------------------------
 180  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 181  */
 182 #if defined(CONFIG_WATCHDOG)
 183 # if defined (CONFIG_IVMS8_16M)
 184 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 185                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 186 #  elif defined (CONFIG_IVMS8_32M)
 187 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 188                          SYPCR_SWE  | SYPCR_SWP)
 189 #  elif defined (CONFIG_IVMS8_64M)
 190 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 191                          SYPCR_SWE  | SYPCR_SWP)
 192 #  endif
 193 #else
 194 # define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 195 #endif
 196
 197 /*-----------------------------------------------------------------------
 198  * SIUMCR - SIU Module Configuration                            11-6
 199  *-----------------------------------------------------------------------
 200  * PCMCIA config., multi-function pin tri-state
 201  */
 202 /* EARB, DBGC and DBPC are initialised by the HCW */
 203 /* => 0x000000C0 */
 204 #define CONFIG_SYS_SIUMCR       (SIUMCR_BSC | SIUMCR_GB5E)
 205
 206 /*-----------------------------------------------------------------------
 207  * TBSCR - Time Base Status and Control                         11-26
 208  *-----------------------------------------------------------------------
 209  * Clear Reference Interrupt Status, Timebase freezing enabled
 210  */
 211 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 212
 213 /*-----------------------------------------------------------------------
 214  * PISCR - Periodic Interrupt Status and Control                11-31
 215  *-----------------------------------------------------------------------
 216  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 217  */
 218 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 219
 220 /*-----------------------------------------------------------------------
 221  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 222  *-----------------------------------------------------------------------
 223  * Reset PLL lock status sticky bit, timer expired status bit and timer
 224  * interrupt status bit, set PLL multiplication factor !
 225  */
 226 /* 0x00B0C0C0 */
 227 #define CONFIG_SYS_PLPRCR                                                       \
 228                 (       (11 << PLPRCR_MF_SHIFT) |                       \
 229                         PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
 230                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 231                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 232                 )
 233
 234 /*-----------------------------------------------------------------------
 235  * SCCR - System Clock and reset Control Register               15-27
 236  *-----------------------------------------------------------------------
 237  * Set clock output, timebase and RTC source and divider,
 238  * power management and some other internal clocks
 239  */
 240 #define SCCR_MASK       SCCR_EBDF11
 241 /* 0x01800014 */
 242 #define CONFIG_SYS_SCCR (SCCR_COM01     | /*SCCR_TBS|*/         \
 243                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 244                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 245                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 246                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 247                          SCCR_DFNH000   |   SCCR_DFLCD101 |     \
 248                          SCCR_DFALCD00)
 249
 250 /*-----------------------------------------------------------------------
 251  * RTCSC - Real-Time Clock Status and Control Register          11-27
 252  *-----------------------------------------------------------------------
 253  */
 254 /* 0x00C3 */
 255 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 256
 257
 258 /*-----------------------------------------------------------------------
 259  * RCCR - RISC Controller Configuration Register                19-4
 260  *-----------------------------------------------------------------------
 261  */
 262 /* TIMEP=2 */
 263 #define CONFIG_SYS_RCCR 0x0200
 264
 265 /*-----------------------------------------------------------------------
 266  * RMDS - RISC Microcode Development Support Control Register
 267  *-----------------------------------------------------------------------
 268  */
 269 #define CONFIG_SYS_RMDS 0
 270
 271 /*-----------------------------------------------------------------------
 272  *
 273  * Interrupt Levels
 274  *-----------------------------------------------------------------------
 275  */
 276 #define CONFIG_SYS_CPM_INTERRUPT        13      /* SIU_LEVEL6   */
 277
 278 /*-----------------------------------------------------------------------
 279  * PCMCIA stuff
 280  *-----------------------------------------------------------------------
 281  *
 282  */
 283 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 284 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 285 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 286 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 287 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 288 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 289 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 290 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 291
 292 /*-----------------------------------------------------------------------
 293  * IDE/ATA stuff
 294  *-----------------------------------------------------------------------
 295  */
 296 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 297 #define CONFIG_IDE_INIT_POSTRESET       1       /* Use postreset IDE hook */
 298 #define CONFIG_IDE_8xx_DIRECT   1       /* PCMCIA interface required    */
 299 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 300
 301 #define CONFIG_SYS_IDE_MAXBUS           1       /* The IVMS8 has only 1 IDE bus */
 302 #define CONFIG_SYS_IDE_MAXDEVICE        1       /*    ... and only 1 IDE device */
 303
 304 #define CONFIG_SYS_ATA_BASE_ADDR        0xFE100000
 305 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 306 #undef  CONFIG_SYS_ATA_IDE1_OFFSET              /* only one IDE bus available   */
 307
 308 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 309 #define CONFIG_SYS_ATA_REG_OFFSET       0x0080  /* Offset for normal register accesses  */
 310 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100  /* Offset for alternate registers       */
 311
 312 /*-----------------------------------------------------------------------
 313  *
 314  *-----------------------------------------------------------------------
 315  *
 316  */
 317 #define CONFIG_SYS_DER  0
 318
 319 /*
 320  * Init Memory Controller:
 321  *
 322  * BR0 and OR0 (FLASH)
 323  */
 324
 325 #define FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank #0        */
 326
 327 /* used to re-map FLASH both when starting from SRAM or FLASH:
 328  * restrict access enough to keep SRAM working (if any)
 329  * but not too much to meddle with FLASH accesses
 330  */
 331 /* EPROMs are 512kb */
 332 #define CONFIG_SYS_REMAP_OR_AM          0xFFF80000      /* OR addr mask */
 333 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000      /* OR addr mask */
 334
 335 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 336 #define CONFIG_SYS_OR_TIMING_FLASH      (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
 337                                  OR_SCY_5_CLK | OR_EHTR)
 338
 339 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 340 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 341 /* 16 bit, bank valid */
 342 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 343
 344 /*
 345  * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
 346  *
 347  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 348  */
 349 #define ELIC_SACCO_BASE         0xFE000000
 350 #define ELIC_SACCO_OR_AM        0xFFFF8000
 351 #define ELIC_SACCO_TIMING       0x00000F26
 352
 353 #define CONFIG_SYS_OR1  (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
 354 #define CONFIG_SYS_BR1  ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 355
 356 /*
 357  * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
 358  *
 359  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 360  */
 361 #define ELIC_EPIC_BASE          0xFE008000
 362 #define ELIC_EPIC_OR_AM         0xFFFF8000
 363 #define ELIC_EPIC_TIMING        0x00000F26
 364
 365 #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
 366 #define CONFIG_SYS_BR2  ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 367
 368 /*
 369  * BR3/OR3: SDRAM
 370  *
 371  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 372  */
 373 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 374 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 375 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 376
 377 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 378
 379 #define CONFIG_SYS_OR3_PRELIM   (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 380 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 381
 382 /*
 383  * BR4/OR4: not used
 384  */
 385
 386 /*
 387  * BR5/OR5: SHARC ADSP-2165L
 388  *
 389  * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 390  */
 391 #define SHARC_BASE              0xFE400000
 392 #define SHARC_OR_AM             0xFFC00000
 393 #define SHARC_TIMING            0x00000700
 394
 395 #define CONFIG_SYS_OR5  (SHARC_OR_AM | SHARC_TIMING )
 396 #define CONFIG_SYS_BR5  ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 397
 398 /*
 399  * Memory Periodic Timer Prescaler
 400  */
 401
 402 /* periodic timer for refresh */
 403 #define CONFIG_SYS_MBMR_PTB     204
 404
 405 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 406 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 407 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 408
 409 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 410 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 411 #if defined (CONFIG_IVMS8_16M)
 412  #define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 413 #elif defined (CONFIG_IVMS8_32M)
 414 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 415 #elif defined (CONFIG_IVMS8_64M)
 416 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8          /* setting for 1 bank   */
 417 #endif
 418
 419
 420 /*
 421  * MBMR settings for SDRAM
 422  */
 423
 424 #if defined (CONFIG_IVMS8_16M)
 425  /* 8 column SDRAM */
 426 # define CONFIG_SYS_MBMR_8COL   ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 427                          MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
 428                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 429 #elif defined (CONFIG_IVMS8_32M)
 430 /* 128 MBit SDRAM */
 431 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 432                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 433                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 434 #elif defined (CONFIG_IVMS8_64M)
 435 /* 128 MBit SDRAM */
 436 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 437                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 438                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 439
 440 #endif
 441 #endif  /* __CONFIG_H */