include/configs/IVMS8.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  37 #define CONFIG_IVMS8            1       /* ...on a IVMS8 board          */
  38
  39 #if defined (CONFIG_IVMS8_16M)
  40 # define CONFIG_IDENT_STRING     " IVMS8"
  41 #elif defined (CONFIG_IVMS8_32M)
  42 # define CONFIG_IDENT_STRING     " IVMS8_128"
  43 #elif defined (CONFIG_IVMS8_64M)
  44 # define CONFIG_IDENT_STRING     " IVMS8_256"
  45 #endif
  46
  47 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  48 #undef  CONFIG_8xx_CONS_SMC2
  49 #undef  CONFIG_8xx_CONS_NONE
  50 #define CONFIG_BAUDRATE         115200
  51
  52 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  53 #define CONFIG_8xx_GCLK_FREQ    50331648
  54
  55 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* Show boot progress on LEDs   */
  56
  57 #if 0
  58 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  59 #else
  60 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  61 #endif
  62 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  63
  64 #define CONFIG_BOOTARGS         "root=/dev/nfs rw "                     \
  65                                 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "   \
  66                                 "nfsaddrs=10.0.0.99:10.0.0.2"
  67
  68 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  69 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  70
  71 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  72
  73 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  74
  75 /*
  76  * Command line configuration.
  77  */
  78 #include <config_cmd_default.h>
  79
  80 #define CONFIG_CMD_IDE
  81
  82
  83 #define CONFIG_MAC_PARTITION
  84 #define CONFIG_DOS_PARTITION
  85
  86 /*
  87  * BOOTP options
  88  */
  89 #define CONFIG_BOOTP_SUBNETMASK
  90 #define CONFIG_BOOTP_HOSTNAME
  91 #define CONFIG_BOOTP_BOOTPATH
  92 #define CONFIG_BOOTP_BOOTFILESIZE
  93
  94
  95 /*
  96  * Miscellaneous configurable options
  97  */
  98 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  99 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 100 #if defined(CONFIG_CMD_KGDB)
 101 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 102 #else
 103 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 104 #endif
 105 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 106 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 107 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 108
 109 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 110 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 111
 112 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 113
 114 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 115
 116 #define CONFIG_SYS_PB_SDRAM_CLKE        0x00008000              /* PB 16        */
 117 #define CONFIG_SYS_PB_ETH_POWERDOWN     0x00010000              /* PB 15        */
 118 #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000              /* PB 14        */
 119
 120 #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010)        /* PC 11        */
 121 #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020)        /* PC 10        */
 122
 123 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 124
 125 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 126
 127 /*
 128  * Low Level Configuration Settings
 129  * (address mappings, register initial values, etc.)
 130  * You should know what you are doing if you make changes here.
 131  */
 132 /*-----------------------------------------------------------------------
 133  * Internal Memory Mapped Register
 134  */
 135 #define CONFIG_SYS_IMMR         0xFFF00000 /* was: 0xFF000000 */
 136
 137 /*-----------------------------------------------------------------------
 138  * Definitions for initial stack pointer and data area (in DPRAM)
 139  */
 140 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 141 #if defined (CONFIG_IVMS8_16M)
 142 # define        CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 143 #elif defined (CONFIG_IVMS8_32M)
 144 # define        CONFIG_SYS_INIT_RAM_END 0x3000  /* End of used area in DPRAM    */
 145 #elif defined (CONFIG_IVMS8_64M)
 146 # define        CONFIG_SYS_INIT_RAM_END 0x3000  /* End of used area in DPRAM    */
 147 #endif
 148
 149 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 150 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 151 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 152
 153 /*-----------------------------------------------------------------------
 154  * Start addresses for the final memory configuration
 155  * (Set up by the startup code)
 156  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 157  */
 158 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 159 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 160 #ifdef  DEBUG
 161 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 162 #else
 163 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 164 #endif
 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 166 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 167
 168 /*
 169  * For booting Linux, the board info and command line data
 170  * have to be in the first 8 MB of memory, since this is
 171  * the maximum mapped by the Linux kernel during initialization.
 172  */
 173 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 174 /*-----------------------------------------------------------------------
 175  * FLASH organization
 176  */
 177 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 178 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 179
 180 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 181 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 182
 183 #define CONFIG_ENV_IS_IN_FLASH  1
 184 #define CONFIG_ENV_OFFSET               0x7A000 /*   Offset   of Environment Sector     */
 185 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 186 /*-----------------------------------------------------------------------
 187  * Cache Configuration
 188  */
 189 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 190 #if defined(CONFIG_CMD_KGDB)
 191 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 192 #endif
 193
 194 /*-----------------------------------------------------------------------
 195  * SYPCR - System Protection Control                            11-9
 196  * SYPCR can only be written once after reset!
 197  *-----------------------------------------------------------------------
 198  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 199  */
 200 #if defined(CONFIG_WATCHDOG)
 201 # if defined (CONFIG_IVMS8_16M)
 202 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 203                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 204 #  elif defined (CONFIG_IVMS8_32M)
 205 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 206                          SYPCR_SWE  | SYPCR_SWP)
 207 #  elif defined (CONFIG_IVMS8_64M)
 208 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 209                          SYPCR_SWE  | SYPCR_SWP)
 210 #  endif
 211 #else
 212 # define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 213 #endif
 214
 215 /*-----------------------------------------------------------------------
 216  * SIUMCR - SIU Module Configuration                            11-6
 217  *-----------------------------------------------------------------------
 218  * PCMCIA config., multi-function pin tri-state
 219  */
 220 /* EARB, DBGC and DBPC are initialised by the HCW */
 221 /* => 0x000000C0 */
 222 #define CONFIG_SYS_SIUMCR       (SIUMCR_BSC | SIUMCR_GB5E)
 223
 224 /*-----------------------------------------------------------------------
 225  * TBSCR - Time Base Status and Control                         11-26
 226  *-----------------------------------------------------------------------
 227  * Clear Reference Interrupt Status, Timebase freezing enabled
 228  */
 229 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 230
 231 /*-----------------------------------------------------------------------
 232  * PISCR - Periodic Interrupt Status and Control                11-31
 233  *-----------------------------------------------------------------------
 234  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 235  */
 236 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 237
 238 /*-----------------------------------------------------------------------
 239  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 240  *-----------------------------------------------------------------------
 241  * Reset PLL lock status sticky bit, timer expired status bit and timer
 242  * interrupt status bit, set PLL multiplication factor !
 243  */
 244 /* 0x00B0C0C0 */
 245 #define CONFIG_SYS_PLPRCR                                                       \
 246                 (       (11 << PLPRCR_MF_SHIFT) |                       \
 247                         PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
 248                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 249                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 250                 )
 251
 252 /*-----------------------------------------------------------------------
 253  * SCCR - System Clock and reset Control Register               15-27
 254  *-----------------------------------------------------------------------
 255  * Set clock output, timebase and RTC source and divider,
 256  * power management and some other internal clocks
 257  */
 258 #define SCCR_MASK       SCCR_EBDF11
 259 /* 0x01800014 */
 260 #define CONFIG_SYS_SCCR (SCCR_COM01     | /*SCCR_TBS|*/         \
 261                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 262                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 263                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 264                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 265                          SCCR_DFNH000   |   SCCR_DFLCD101 |     \
 266                          SCCR_DFALCD00)
 267
 268 /*-----------------------------------------------------------------------
 269  * RTCSC - Real-Time Clock Status and Control Register          11-27
 270  *-----------------------------------------------------------------------
 271  */
 272 /* 0x00C3 */
 273 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 274
 275
 276 /*-----------------------------------------------------------------------
 277  * RCCR - RISC Controller Configuration Register                19-4
 278  *-----------------------------------------------------------------------
 279  */
 280 /* TIMEP=2 */
 281 #define CONFIG_SYS_RCCR 0x0200
 282
 283 /*-----------------------------------------------------------------------
 284  * RMDS - RISC Microcode Development Support Control Register
 285  *-----------------------------------------------------------------------
 286  */
 287 #define CONFIG_SYS_RMDS 0
 288
 289 /*-----------------------------------------------------------------------
 290  *
 291  * Interrupt Levels
 292  *-----------------------------------------------------------------------
 293  */
 294 #define CONFIG_SYS_CPM_INTERRUPT        13      /* SIU_LEVEL6   */
 295
 296 /*-----------------------------------------------------------------------
 297  * PCMCIA stuff
 298  *-----------------------------------------------------------------------
 299  *
 300  */
 301 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 302 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 303 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 304 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 305 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 306 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 307 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 308 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 309
 310 /*-----------------------------------------------------------------------
 311  * IDE/ATA stuff
 312  *-----------------------------------------------------------------------
 313  */
 314 #define CONFIG_IDE_8xx_DIRECT   1       /* PCMCIA interface required    */
 315 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 316
 317 #define CONFIG_SYS_IDE_MAXBUS           1       /* The IVMS8 has only 1 IDE bus */
 318 #define CONFIG_SYS_IDE_MAXDEVICE        1       /*    ... and only 1 IDE device */
 319
 320 #define CONFIG_SYS_ATA_BASE_ADDR        0xFE100000
 321 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 322 #undef  CONFIG_SYS_ATA_IDE1_OFFSET              /* only one IDE bus available   */
 323
 324 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 325 #define CONFIG_SYS_ATA_REG_OFFSET       0x0080  /* Offset for normal register accesses  */
 326 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100  /* Offset for alternate registers       */
 327
 328 /*-----------------------------------------------------------------------
 329  *
 330  *-----------------------------------------------------------------------
 331  *
 332  */
 333 #define CONFIG_SYS_DER  0
 334
 335 /*
 336  * Init Memory Controller:
 337  *
 338  * BR0 and OR0 (FLASH)
 339  */
 340
 341 #define FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank #0        */
 342
 343 /* used to re-map FLASH both when starting from SRAM or FLASH:
 344  * restrict access enough to keep SRAM working (if any)
 345  * but not too much to meddle with FLASH accesses
 346  */
 347 /* EPROMs are 512kb */
 348 #define CONFIG_SYS_REMAP_OR_AM          0xFFF80000      /* OR addr mask */
 349 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000      /* OR addr mask */
 350
 351 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 352 #define CONFIG_SYS_OR_TIMING_FLASH      (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
 353                                  OR_SCY_5_CLK | OR_EHTR)
 354
 355 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 356 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 357 /* 16 bit, bank valid */
 358 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 359
 360 /*
 361  * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
 362  *
 363  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 364  */
 365 #define ELIC_SACCO_BASE         0xFE000000
 366 #define ELIC_SACCO_OR_AM        0xFFFF8000
 367 #define ELIC_SACCO_TIMING       0x00000F26
 368
 369 #define CONFIG_SYS_OR1  (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
 370 #define CONFIG_SYS_BR1  ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 371
 372 /*
 373  * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
 374  *
 375  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 376  */
 377 #define ELIC_EPIC_BASE          0xFE008000
 378 #define ELIC_EPIC_OR_AM         0xFFFF8000
 379 #define ELIC_EPIC_TIMING        0x00000F26
 380
 381 #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
 382 #define CONFIG_SYS_BR2  ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 383
 384 /*
 385  * BR3/OR3: SDRAM
 386  *
 387  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 388  */
 389 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 390 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 391 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 392
 393 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 394
 395 #define CONFIG_SYS_OR3_PRELIM   (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 396 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 397
 398 /*
 399  * BR4/OR4: not used
 400  */
 401
 402 /*
 403  * BR5/OR5: SHARC ADSP-2165L
 404  *
 405  * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 406  */
 407 #define SHARC_BASE              0xFE400000
 408 #define SHARC_OR_AM             0xFFC00000
 409 #define SHARC_TIMING            0x00000700
 410
 411 #define CONFIG_SYS_OR5  (SHARC_OR_AM | SHARC_TIMING )
 412 #define CONFIG_SYS_BR5  ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 413
 414 /*
 415  * Memory Periodic Timer Prescaler
 416  */
 417
 418 /* periodic timer for refresh */
 419 #define CONFIG_SYS_MBMR_PTB     204
 420
 421 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 422 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 423 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 424
 425 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 426 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 427 #if defined (CONFIG_IVMS8_16M)
 428  #define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 429 #elif defined (CONFIG_IVMS8_32M)
 430 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 431 #elif defined (CONFIG_IVMS8_64M)
 432 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8          /* setting for 1 bank   */
 433 #endif
 434
 435
 436 /*
 437  * MBMR settings for SDRAM
 438  */
 439
 440 #if defined (CONFIG_IVMS8_16M)
 441  /* 8 column SDRAM */
 442 # define CONFIG_SYS_MBMR_8COL   ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 443                          MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
 444                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 445 #elif defined (CONFIG_IVMS8_32M)
 446 /* 128 MBit SDRAM */
 447 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 448                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 449                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 450 #elif defined (CONFIG_IVMS8_64M)
 451 /* 128 MBit SDRAM */
 452 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 453                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 454                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 455
 456 #endif
 457
 458 /*
 459  * Internal Definitions
 460  *
 461  * Boot Flags
 462  */
 463 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 464 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 465
 466 #endif  /* __CONFIG_H */