include/configs/IVMS8.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  37 #define CONFIG_IVMS8            1       /* ...on a IVMS8 board          */
  38
  39 #if defined (CONFIG_IVMS8_16M)
  40 # define CONFIG_IDENT_STRING     " IVMS8"
  41 #elif defined (CONFIG_IVMS8_32M)
  42 # define CONFIG_IDENT_STRING     " IVMS8_128"
  43 #elif defined (CONFIG_IVMS8_64M)
  44 # define CONFIG_IDENT_STRING     " IVMS8_256"
  45 #endif
  46
  47 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  48 #undef  CONFIG_8xx_CONS_SMC2
  49 #undef  CONFIG_8xx_CONS_NONE
  50 #define CONFIG_BAUDRATE         115200
  51
  52 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  53
  54 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  55 #define CONFIG_8xx_GCLK_FREQ    50331648
  56
  57 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* Show boot progress on LEDs   */
  58
  59 #if 0
  60 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  61 #else
  62 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  63 #endif
  64 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  65
  66 #define CONFIG_BOOTARGS         "root=/dev/nfs rw "                     \
  67                                 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "   \
  68                                 "nfsaddrs=10.0.0.99:10.0.0.2"
  69
  70 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  71 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  72
  73 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  74
  75 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  76
  77 /*
  78  * Command line configuration.
  79  */
  80 #include <config_cmd_default.h>
  81
  82 #define CONFIG_CMD_IDE
  83
  84
  85 #define CONFIG_MAC_PARTITION
  86 #define CONFIG_DOS_PARTITION
  87
  88 /*
  89  * BOOTP options
  90  */
  91 #define CONFIG_BOOTP_SUBNETMASK
  92 #define CONFIG_BOOTP_HOSTNAME
  93 #define CONFIG_BOOTP_BOOTPATH
  94 #define CONFIG_BOOTP_BOOTFILESIZE
  95
  96
  97 /*
  98  * Miscellaneous configurable options
  99  */
 100 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 101 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 102 #if defined(CONFIG_CMD_KGDB)
 103 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 104 #else
 105 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 106 #endif
 107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 108 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 109 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 110
 111 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 112 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 113
 114 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 115
 116 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 117
 118 #define CONFIG_SYS_PB_SDRAM_CLKE        0x00008000              /* PB 16        */
 119 #define CONFIG_SYS_PB_ETH_POWERDOWN     0x00010000              /* PB 15        */
 120 #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000              /* PB 14        */
 121
 122 #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010)        /* PC 11        */
 123 #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020)        /* PC 10        */
 124
 125 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 126
 127 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 128
 129 /*
 130  * Low Level Configuration Settings
 131  * (address mappings, register initial values, etc.)
 132  * You should know what you are doing if you make changes here.
 133  */
 134 /*-----------------------------------------------------------------------
 135  * Internal Memory Mapped Register
 136  */
 137 #define CONFIG_SYS_IMMR         0xFFF00000 /* was: 0xFF000000 */
 138
 139 /*-----------------------------------------------------------------------
 140  * Definitions for initial stack pointer and data area (in DPRAM)
 141  */
 142 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 143 #if defined (CONFIG_IVMS8_16M)
 144 # define        CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 145 #elif defined (CONFIG_IVMS8_32M)
 146 # define        CONFIG_SYS_INIT_RAM_END 0x3000  /* End of used area in DPRAM    */
 147 #elif defined (CONFIG_IVMS8_64M)
 148 # define        CONFIG_SYS_INIT_RAM_END 0x3000  /* End of used area in DPRAM    */
 149 #endif
 150
 151 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 152 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 153 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 154
 155 /*-----------------------------------------------------------------------
 156  * Start addresses for the final memory configuration
 157  * (Set up by the startup code)
 158  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 159  */
 160 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 161 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 162 #ifdef  DEBUG
 163 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 164 #else
 165 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 166 #endif
 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 168 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 169
 170 /*
 171  * For booting Linux, the board info and command line data
 172  * have to be in the first 8 MB of memory, since this is
 173  * the maximum mapped by the Linux kernel during initialization.
 174  */
 175 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 176 /*-----------------------------------------------------------------------
 177  * FLASH organization
 178  */
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 180 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 181
 182 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 183 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 184
 185 #define CONFIG_ENV_IS_IN_FLASH  1
 186 #define CONFIG_ENV_OFFSET               0x7A000 /*   Offset   of Environment Sector     */
 187 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 188 /*-----------------------------------------------------------------------
 189  * Cache Configuration
 190  */
 191 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 192 #if defined(CONFIG_CMD_KGDB)
 193 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 194 #endif
 195
 196 /*-----------------------------------------------------------------------
 197  * SYPCR - System Protection Control                            11-9
 198  * SYPCR can only be written once after reset!
 199  *-----------------------------------------------------------------------
 200  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 201  */
 202 #if defined(CONFIG_WATCHDOG)
 203 # if defined (CONFIG_IVMS8_16M)
 204 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 205                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 206 #  elif defined (CONFIG_IVMS8_32M)
 207 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 208                          SYPCR_SWE  | SYPCR_SWP)
 209 #  elif defined (CONFIG_IVMS8_64M)
 210 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 211                          SYPCR_SWE  | SYPCR_SWP)
 212 #  endif
 213 #else
 214 # define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 215 #endif
 216
 217 /*-----------------------------------------------------------------------
 218  * SIUMCR - SIU Module Configuration                            11-6
 219  *-----------------------------------------------------------------------
 220  * PCMCIA config., multi-function pin tri-state
 221  */
 222 /* EARB, DBGC and DBPC are initialised by the HCW */
 223 /* => 0x000000C0 */
 224 #define CONFIG_SYS_SIUMCR       (SIUMCR_BSC | SIUMCR_GB5E)
 225
 226 /*-----------------------------------------------------------------------
 227  * TBSCR - Time Base Status and Control                         11-26
 228  *-----------------------------------------------------------------------
 229  * Clear Reference Interrupt Status, Timebase freezing enabled
 230  */
 231 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 232
 233 /*-----------------------------------------------------------------------
 234  * PISCR - Periodic Interrupt Status and Control                11-31
 235  *-----------------------------------------------------------------------
 236  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 237  */
 238 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 239
 240 /*-----------------------------------------------------------------------
 241  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 242  *-----------------------------------------------------------------------
 243  * Reset PLL lock status sticky bit, timer expired status bit and timer
 244  * interrupt status bit, set PLL multiplication factor !
 245  */
 246 /* 0x00B0C0C0 */
 247 #define CONFIG_SYS_PLPRCR                                                       \
 248                 (       (11 << PLPRCR_MF_SHIFT) |                       \
 249                         PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
 250                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 251                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 252                 )
 253
 254 /*-----------------------------------------------------------------------
 255  * SCCR - System Clock and reset Control Register               15-27
 256  *-----------------------------------------------------------------------
 257  * Set clock output, timebase and RTC source and divider,
 258  * power management and some other internal clocks
 259  */
 260 #define SCCR_MASK       SCCR_EBDF11
 261 /* 0x01800014 */
 262 #define CONFIG_SYS_SCCR (SCCR_COM01     | /*SCCR_TBS|*/         \
 263                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 264                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 265                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 266                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 267                          SCCR_DFNH000   |   SCCR_DFLCD101 |     \
 268                          SCCR_DFALCD00)
 269
 270 /*-----------------------------------------------------------------------
 271  * RTCSC - Real-Time Clock Status and Control Register          11-27
 272  *-----------------------------------------------------------------------
 273  */
 274 /* 0x00C3 */
 275 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 276
 277
 278 /*-----------------------------------------------------------------------
 279  * RCCR - RISC Controller Configuration Register                19-4
 280  *-----------------------------------------------------------------------
 281  */
 282 /* TIMEP=2 */
 283 #define CONFIG_SYS_RCCR 0x0200
 284
 285 /*-----------------------------------------------------------------------
 286  * RMDS - RISC Microcode Development Support Control Register
 287  *-----------------------------------------------------------------------
 288  */
 289 #define CONFIG_SYS_RMDS 0
 290
 291 /*-----------------------------------------------------------------------
 292  *
 293  * Interrupt Levels
 294  *-----------------------------------------------------------------------
 295  */
 296 #define CONFIG_SYS_CPM_INTERRUPT        13      /* SIU_LEVEL6   */
 297
 298 /*-----------------------------------------------------------------------
 299  * PCMCIA stuff
 300  *-----------------------------------------------------------------------
 301  *
 302  */
 303 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 304 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 305 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 306 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 307 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 308 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 309 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 310 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 311
 312 /*-----------------------------------------------------------------------
 313  * IDE/ATA stuff
 314  *-----------------------------------------------------------------------
 315  */
 316 #define CONFIG_IDE_8xx_DIRECT   1       /* PCMCIA interface required    */
 317 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 318
 319 #define CONFIG_SYS_IDE_MAXBUS           1       /* The IVMS8 has only 1 IDE bus */
 320 #define CONFIG_SYS_IDE_MAXDEVICE        1       /*    ... and only 1 IDE device */
 321
 322 #define CONFIG_SYS_ATA_BASE_ADDR        0xFE100000
 323 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 324 #undef  CONFIG_SYS_ATA_IDE1_OFFSET              /* only one IDE bus available   */
 325
 326 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 327 #define CONFIG_SYS_ATA_REG_OFFSET       0x0080  /* Offset for normal register accesses  */
 328 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100  /* Offset for alternate registers       */
 329
 330 /*-----------------------------------------------------------------------
 331  *
 332  *-----------------------------------------------------------------------
 333  *
 334  */
 335 #define CONFIG_SYS_DER  0
 336
 337 /*
 338  * Init Memory Controller:
 339  *
 340  * BR0 and OR0 (FLASH)
 341  */
 342
 343 #define FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank #0        */
 344
 345 /* used to re-map FLASH both when starting from SRAM or FLASH:
 346  * restrict access enough to keep SRAM working (if any)
 347  * but not too much to meddle with FLASH accesses
 348  */
 349 /* EPROMs are 512kb */
 350 #define CONFIG_SYS_REMAP_OR_AM          0xFFF80000      /* OR addr mask */
 351 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000      /* OR addr mask */
 352
 353 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 354 #define CONFIG_SYS_OR_TIMING_FLASH      (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
 355                                  OR_SCY_5_CLK | OR_EHTR)
 356
 357 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 358 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 359 /* 16 bit, bank valid */
 360 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 361
 362 /*
 363  * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
 364  *
 365  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 366  */
 367 #define ELIC_SACCO_BASE         0xFE000000
 368 #define ELIC_SACCO_OR_AM        0xFFFF8000
 369 #define ELIC_SACCO_TIMING       0x00000F26
 370
 371 #define CONFIG_SYS_OR1  (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
 372 #define CONFIG_SYS_BR1  ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 373
 374 /*
 375  * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
 376  *
 377  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 378  */
 379 #define ELIC_EPIC_BASE          0xFE008000
 380 #define ELIC_EPIC_OR_AM         0xFFFF8000
 381 #define ELIC_EPIC_TIMING        0x00000F26
 382
 383 #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
 384 #define CONFIG_SYS_BR2  ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 385
 386 /*
 387  * BR3/OR3: SDRAM
 388  *
 389  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 390  */
 391 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 392 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 393 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 394
 395 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 396
 397 #define CONFIG_SYS_OR3_PRELIM   (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 398 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 399
 400 /*
 401  * BR4/OR4: not used
 402  */
 403
 404 /*
 405  * BR5/OR5: SHARC ADSP-2165L
 406  *
 407  * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 408  */
 409 #define SHARC_BASE              0xFE400000
 410 #define SHARC_OR_AM             0xFFC00000
 411 #define SHARC_TIMING            0x00000700
 412
 413 #define CONFIG_SYS_OR5  (SHARC_OR_AM | SHARC_TIMING )
 414 #define CONFIG_SYS_BR5  ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 415
 416 /*
 417  * Memory Periodic Timer Prescaler
 418  */
 419
 420 /* periodic timer for refresh */
 421 #define CONFIG_SYS_MBMR_PTB     204
 422
 423 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 424 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 425 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 426
 427 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 428 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 429 #if defined (CONFIG_IVMS8_16M)
 430  #define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 431 #elif defined (CONFIG_IVMS8_32M)
 432 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 433 #elif defined (CONFIG_IVMS8_64M)
 434 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8          /* setting for 1 bank   */
 435 #endif
 436
 437
 438 /*
 439  * MBMR settings for SDRAM
 440  */
 441
 442 #if defined (CONFIG_IVMS8_16M)
 443  /* 8 column SDRAM */
 444 # define CONFIG_SYS_MBMR_8COL   ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 445                          MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
 446                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 447 #elif defined (CONFIG_IVMS8_32M)
 448 /* 128 MBit SDRAM */
 449 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 450                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 451                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 452 #elif defined (CONFIG_IVMS8_64M)
 453 /* 128 MBit SDRAM */
 454 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 455                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 456                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 457
 458 #endif
 459
 460 /*
 461  * Internal Definitions
 462  *
 463  * Boot Flags
 464  */
 465 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 466 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 467
 468 #endif  /* __CONFIG_H */