include/configs/IVMS8.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  37 #define CONFIG_IVMS8            1       /* ...on a IVMS8 board          */
  38
  39 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  40
  41 #if defined (CONFIG_IVMS8_16M)
  42 # define CONFIG_IDENT_STRING     " IVMS8"
  43 #elif defined (CONFIG_IVMS8_32M)
  44 # define CONFIG_IDENT_STRING     " IVMS8_128"
  45 #elif defined (CONFIG_IVMS8_64M)
  46 # define CONFIG_IDENT_STRING     " IVMS8_256"
  47 #endif
  48
  49 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  50 #undef  CONFIG_8xx_CONS_SMC2
  51 #undef  CONFIG_8xx_CONS_NONE
  52 #define CONFIG_BAUDRATE         115200
  53
  54 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  55
  56 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  57 #define CONFIG_8xx_GCLK_FREQ    50331648
  58
  59 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* Show boot progress on LEDs   */
  60
  61 #if 0
  62 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  63 #else
  64 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  65 #endif
  66 #define CONFIG_BOOTCOMMAND      "bootp" /* autoboot command             */
  67
  68 #define CONFIG_BOOTARGS         "root=/dev/nfs rw "                     \
  69                                 "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "   \
  70                                 "nfsaddrs=10.0.0.99:10.0.0.2"
  71
  72 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  73 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_IDE
  85
  86
  87 #define CONFIG_MAC_PARTITION
  88 #define CONFIG_DOS_PARTITION
  89
  90 /*
  91  * BOOTP options
  92  */
  93 #define CONFIG_BOOTP_SUBNETMASK
  94 #define CONFIG_BOOTP_HOSTNAME
  95 #define CONFIG_BOOTP_BOOTPATH
  96 #define CONFIG_BOOTP_BOOTFILESIZE
  97
  98
  99 /*
 100  * Miscellaneous configurable options
 101  */
 102 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 103 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 104 #if defined(CONFIG_CMD_KGDB)
 105 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 106 #else
 107 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 108 #endif
 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 110 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 111 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 112
 113 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 114 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 115
 116 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 117
 118 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 119
 120 #define CONFIG_SYS_PB_SDRAM_CLKE        0x00008000              /* PB 16        */
 121 #define CONFIG_SYS_PB_ETH_POWERDOWN     0x00010000              /* PB 15        */
 122 #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000              /* PB 14        */
 123
 124 #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010)        /* PC 11        */
 125 #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020)        /* PC 10        */
 126
 127 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 128
 129 /*
 130  * Low Level Configuration Settings
 131  * (address mappings, register initial values, etc.)
 132  * You should know what you are doing if you make changes here.
 133  */
 134 /*-----------------------------------------------------------------------
 135  * Internal Memory Mapped Register
 136  */
 137 #define CONFIG_SYS_IMMR         0xFFF00000 /* was: 0xFF000000 */
 138
 139 /*-----------------------------------------------------------------------
 140  * Definitions for initial stack pointer and data area (in DPRAM)
 141  */
 142 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 143 #if defined (CONFIG_IVMS8_16M)
 144 # define        CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 145 #elif defined (CONFIG_IVMS8_32M)
 146 # define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 147 #elif defined (CONFIG_IVMS8_64M)
 148 # define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 149 #endif
 150
 151 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 152 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 153
 154 /*-----------------------------------------------------------------------
 155  * Start addresses for the final memory configuration
 156  * (Set up by the startup code)
 157  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 158  */
 159 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 160 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 161 #ifdef  DEBUG
 162 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 163 #else
 164 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 165 #endif
 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 167 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 168
 169 /*
 170  * For booting Linux, the board info and command line data
 171  * have to be in the first 8 MB of memory, since this is
 172  * the maximum mapped by the Linux kernel during initialization.
 173  */
 174 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 175 /*-----------------------------------------------------------------------
 176  * FLASH organization
 177  */
 178 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 179 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 180
 181 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 182 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 183
 184 #define CONFIG_ENV_IS_IN_FLASH  1
 185 #define CONFIG_ENV_OFFSET               0x7A000 /*   Offset   of Environment Sector     */
 186 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 187 /*-----------------------------------------------------------------------
 188  * Cache Configuration
 189  */
 190 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 191 #if defined(CONFIG_CMD_KGDB)
 192 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 193 #endif
 194
 195 /*-----------------------------------------------------------------------
 196  * SYPCR - System Protection Control                            11-9
 197  * SYPCR can only be written once after reset!
 198  *-----------------------------------------------------------------------
 199  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 200  */
 201 #if defined(CONFIG_WATCHDOG)
 202 # if defined (CONFIG_IVMS8_16M)
 203 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 204                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 205 #  elif defined (CONFIG_IVMS8_32M)
 206 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 207                          SYPCR_SWE  | SYPCR_SWP)
 208 #  elif defined (CONFIG_IVMS8_64M)
 209 #   define CONFIG_SYS_SYPCR     (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 210                          SYPCR_SWE  | SYPCR_SWP)
 211 #  endif
 212 #else
 213 # define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 214 #endif
 215
 216 /*-----------------------------------------------------------------------
 217  * SIUMCR - SIU Module Configuration                            11-6
 218  *-----------------------------------------------------------------------
 219  * PCMCIA config., multi-function pin tri-state
 220  */
 221 /* EARB, DBGC and DBPC are initialised by the HCW */
 222 /* => 0x000000C0 */
 223 #define CONFIG_SYS_SIUMCR       (SIUMCR_BSC | SIUMCR_GB5E)
 224
 225 /*-----------------------------------------------------------------------
 226  * TBSCR - Time Base Status and Control                         11-26
 227  *-----------------------------------------------------------------------
 228  * Clear Reference Interrupt Status, Timebase freezing enabled
 229  */
 230 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 231
 232 /*-----------------------------------------------------------------------
 233  * PISCR - Periodic Interrupt Status and Control                11-31
 234  *-----------------------------------------------------------------------
 235  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 236  */
 237 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 238
 239 /*-----------------------------------------------------------------------
 240  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 241  *-----------------------------------------------------------------------
 242  * Reset PLL lock status sticky bit, timer expired status bit and timer
 243  * interrupt status bit, set PLL multiplication factor !
 244  */
 245 /* 0x00B0C0C0 */
 246 #define CONFIG_SYS_PLPRCR                                                       \
 247                 (       (11 << PLPRCR_MF_SHIFT) |                       \
 248                         PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
 249                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 250                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 251                 )
 252
 253 /*-----------------------------------------------------------------------
 254  * SCCR - System Clock and reset Control Register               15-27
 255  *-----------------------------------------------------------------------
 256  * Set clock output, timebase and RTC source and divider,
 257  * power management and some other internal clocks
 258  */
 259 #define SCCR_MASK       SCCR_EBDF11
 260 /* 0x01800014 */
 261 #define CONFIG_SYS_SCCR (SCCR_COM01     | /*SCCR_TBS|*/         \
 262                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 263                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 264                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 265                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 266                          SCCR_DFNH000   |   SCCR_DFLCD101 |     \
 267                          SCCR_DFALCD00)
 268
 269 /*-----------------------------------------------------------------------
 270  * RTCSC - Real-Time Clock Status and Control Register          11-27
 271  *-----------------------------------------------------------------------
 272  */
 273 /* 0x00C3 */
 274 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 275
 276
 277 /*-----------------------------------------------------------------------
 278  * RCCR - RISC Controller Configuration Register                19-4
 279  *-----------------------------------------------------------------------
 280  */
 281 /* TIMEP=2 */
 282 #define CONFIG_SYS_RCCR 0x0200
 283
 284 /*-----------------------------------------------------------------------
 285  * RMDS - RISC Microcode Development Support Control Register
 286  *-----------------------------------------------------------------------
 287  */
 288 #define CONFIG_SYS_RMDS 0
 289
 290 /*-----------------------------------------------------------------------
 291  *
 292  * Interrupt Levels
 293  *-----------------------------------------------------------------------
 294  */
 295 #define CONFIG_SYS_CPM_INTERRUPT        13      /* SIU_LEVEL6   */
 296
 297 /*-----------------------------------------------------------------------
 298  * PCMCIA stuff
 299  *-----------------------------------------------------------------------
 300  *
 301  */
 302 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 303 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 304 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 305 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 306 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 307 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 308 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 309 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 310
 311 /*-----------------------------------------------------------------------
 312  * IDE/ATA stuff
 313  *-----------------------------------------------------------------------
 314  */
 315 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 316 #define CONFIG_IDE_INIT_POSTRESET       1       /* Use postreset IDE hook */
 317 #define CONFIG_IDE_8xx_DIRECT   1       /* PCMCIA interface required    */
 318 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 319
 320 #define CONFIG_SYS_IDE_MAXBUS           1       /* The IVMS8 has only 1 IDE bus */
 321 #define CONFIG_SYS_IDE_MAXDEVICE        1       /*    ... and only 1 IDE device */
 322
 323 #define CONFIG_SYS_ATA_BASE_ADDR        0xFE100000
 324 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 325 #undef  CONFIG_SYS_ATA_IDE1_OFFSET              /* only one IDE bus available   */
 326
 327 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 328 #define CONFIG_SYS_ATA_REG_OFFSET       0x0080  /* Offset for normal register accesses  */
 329 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100  /* Offset for alternate registers       */
 330
 331 /*-----------------------------------------------------------------------
 332  *
 333  *-----------------------------------------------------------------------
 334  *
 335  */
 336 #define CONFIG_SYS_DER  0
 337
 338 /*
 339  * Init Memory Controller:
 340  *
 341  * BR0 and OR0 (FLASH)
 342  */
 343
 344 #define FLASH_BASE0_PRELIM      0xFF000000      /* FLASH bank #0        */
 345
 346 /* used to re-map FLASH both when starting from SRAM or FLASH:
 347  * restrict access enough to keep SRAM working (if any)
 348  * but not too much to meddle with FLASH accesses
 349  */
 350 /* EPROMs are 512kb */
 351 #define CONFIG_SYS_REMAP_OR_AM          0xFFF80000      /* OR addr mask */
 352 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000      /* OR addr mask */
 353
 354 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 355 #define CONFIG_SYS_OR_TIMING_FLASH      (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
 356                                  OR_SCY_5_CLK | OR_EHTR)
 357
 358 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 359 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 360 /* 16 bit, bank valid */
 361 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 362
 363 /*
 364  * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
 365  *
 366  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 367  */
 368 #define ELIC_SACCO_BASE         0xFE000000
 369 #define ELIC_SACCO_OR_AM        0xFFFF8000
 370 #define ELIC_SACCO_TIMING       0x00000F26
 371
 372 #define CONFIG_SYS_OR1  (ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
 373 #define CONFIG_SYS_BR1  ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 374
 375 /*
 376  * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
 377  *
 378  * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 379  */
 380 #define ELIC_EPIC_BASE          0xFE008000
 381 #define ELIC_EPIC_OR_AM         0xFFFF8000
 382 #define ELIC_EPIC_TIMING        0x00000F26
 383
 384 #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
 385 #define CONFIG_SYS_BR2  ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 386
 387 /*
 388  * BR3/OR3: SDRAM
 389  *
 390  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 391  */
 392 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 393 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 394 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 395
 396 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 397
 398 #define CONFIG_SYS_OR3_PRELIM   (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 399 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
 400
 401 /*
 402  * BR4/OR4: not used
 403  */
 404
 405 /*
 406  * BR5/OR5: SHARC ADSP-2165L
 407  *
 408  * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 409  */
 410 #define SHARC_BASE              0xFE400000
 411 #define SHARC_OR_AM             0xFFC00000
 412 #define SHARC_TIMING            0x00000700
 413
 414 #define CONFIG_SYS_OR5  (SHARC_OR_AM | SHARC_TIMING )
 415 #define CONFIG_SYS_BR5  ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
 416
 417 /*
 418  * Memory Periodic Timer Prescaler
 419  */
 420
 421 /* periodic timer for refresh */
 422 #define CONFIG_SYS_MBMR_PTB     204
 423
 424 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 425 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 426 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 427
 428 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 429 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 430 #if defined (CONFIG_IVMS8_16M)
 431  #define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 432 #elif defined (CONFIG_IVMS8_32M)
 433 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 434 #elif defined (CONFIG_IVMS8_64M)
 435 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8          /* setting for 1 bank   */
 436 #endif
 437
 438
 439 /*
 440  * MBMR settings for SDRAM
 441  */
 442
 443 #if defined (CONFIG_IVMS8_16M)
 444  /* 8 column SDRAM */
 445 # define CONFIG_SYS_MBMR_8COL   ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 446                          MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
 447                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 448 #elif defined (CONFIG_IVMS8_32M)
 449 /* 128 MBit SDRAM */
 450 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 451                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 452                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 453 #elif defined (CONFIG_IVMS8_64M)
 454 /* 128 MBit SDRAM */
 455 #define CONFIG_SYS_MBMR_8COL    ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
 456                          MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 457                          MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 458
 459 #endif
 460 #endif  /* __CONFIG_H */