include/configs/JSE.h

   1 /*
   2  * (C) Copyright 2003 Picture Elements, Inc.
   3  * Stephen Williams <steve@icarus.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options for the JSE board
  17  * (Theoretically easy to change, but the board is fixed.)
  18  */
  19
  20 #define CONFIG_JSE 1
  21   /* JSE has a PPC405GPr */
  22 #define CONFIG_405GP 1
  23   /* ... with a 33MHz OSC. connected to the SysCLK input */
  24 #define CONFIG_SYS_CLK_FREQ     33333333
  25   /* ... with on-chip memory here (4KBytes) */
  26 #define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
  27 #define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
  28   /* Do not set up locked dcache as init ram. */
  29 #undef CONFIG_SYS_INIT_DCACHE_CS
  30
  31 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  32
  33   /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
  34 #define CONFIG_SYSTEMACE 1
  35 #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
  36 #define CONFIG_SYS_SYSTEMACE_WIDTH 8
  37 #define CONFIG_DOS_PARTITION 1
  38
  39   /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
  40 #define CONFIG_SYS_TEMP_STACK_OCM 1
  41   /* ... place INIT RAM in the OCM address */
  42 # define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR
  43   /* ... give it the whole init ram */
  44 # define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE
  45   /* ... Shave a bit off the end for global data */
  46 # define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  47   /* ... and place the stack pointer at the top of what's left. */
  48 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
  49
  50   /* Enable board_pre_init function */
  51 #define CONFIG_BOARD_PRE_INIT   1
  52 #define CONFIG_BOARD_EARLY_INIT_F 1
  53   /* Disable post-clk setup init function */
  54 #undef CONFIG_BOARD_POSTCLK_INIT
  55   /* Disable call to post_init_f: late init function. */
  56 #undef CONFIG_POST
  57   /* Enable DRAM test. */
  58 #define CONFIG_SYS_DRAM_TEST 1
  59   /* Enable misc_init_r function. */
  60 #define CONFIG_MISC_INIT_R 1
  61
  62   /* JSE has EEPROM chips that are good for environment. */
  63 #undef  CONFIG_ENV_IS_IN_NVRAM
  64 #undef  CONFIG_ENV_IS_IN_FLASH
  65 #define CONFIG_ENV_IS_IN_EEPROM 1
  66 #undef  CONFIG_ENV_IS_NOWHERE
  67
  68   /* This is the 7bit address of the device, not including P. */
  69 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  70   /* After the device address, need one more address byte. */
  71 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  72   /* The EEPROM is 512 bytes. */
  73 #define CONFIG_SYS_EEPROM_SIZE 512
  74   /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
  75 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  76 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  77   /* Put the environment in the second half. */
  78 #define CONFIG_ENV_OFFSET       0x00
  79 #define CONFIG_ENV_SIZE 512
  80
  81   /* The JSE connects UART1 to the console tap connector. */
  82 #define CONFIG_CONS_INDEX       2
  83 #define CONFIG_SYS_NS16550
  84 #define CONFIG_SYS_NS16550_SERIAL
  85 #define CONFIG_SYS_NS16550_REG_SIZE     1
  86 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  87
  88   /* Set console baudrate to 9600 */
  89 #define CONFIG_BAUDRATE         9600
  90
  91 /*
  92  * Configuration related to auto-boot.
  93  *
  94  * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
  95  * before resorting to autoboot. This value can be overridden by the
  96  * bootdelay environment variable.
  97  *
  98  * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
  99  * user that an autoboot will happen.
 100  *
 101  * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
 102  * execute to boot the JSE. This loads the uimage and initrd.img files
 103  * from CompactFlash into memory, then boots them from memory.
 104  *
 105  * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
 106  * it going on the JSE.
 107  */
 108 #define CONFIG_BOOTDELAY        5
 109 #define CONFIG_BOOTARGS         "root=/dev/ram0 init=/linuxrc rw"
 110 #define CONFIG_BOOTCOMMAND      "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
 111
 112
 113 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 114 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 115
 116 #define CONFIG_PPC4xx_EMAC
 117 #define CONFIG_MII              1       /* MII PHY management           */
 118 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 119
 120
 121 /*
 122  * BOOTP options
 123  */
 124 #define CONFIG_BOOTP_BOOTFILESIZE
 125 #define CONFIG_BOOTP_BOOTPATH
 126 #define CONFIG_BOOTP_GATEWAY
 127 #define CONFIG_BOOTP_HOSTNAME
 128
 129
 130 /*
 131  * Command line configuration.
 132  */
 133 #include <config_cmd_default.h>
 134
 135 #define CONFIG_CMD_DHCP
 136 #define CONFIG_CMD_EEPROM
 137 #define CONFIG_CMD_ELF
 138 #define CONFIG_CMD_FAT
 139 #define CONFIG_CMD_FLASH
 140 #define CONFIG_CMD_IRQ
 141 #define CONFIG_CMD_MII
 142 #define CONFIG_CMD_NET
 143 #define CONFIG_CMD_PCI
 144 #define CONFIG_CMD_PING
 145
 146
 147   /* watchdog disabled */
 148 #undef CONFIG_WATCHDOG
 149   /* SPD EEPROM (sdram speed config) disabled */
 150 #undef CONFIG_SPD_EEPROM
 151 #undef SPD_EEPROM_ADDRESS
 152
 153 /*
 154  * Miscellaneous configurable options
 155  */
 156 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 157
 158 #define CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 159
 160 #if defined(CONFIG_CMD_KGDB)
 161 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 162 #else
 163 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 164 #endif
 165 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 166 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 167 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 168
 169 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 170 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 171
 172 /*
 173  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 174  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 175  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 176  * The Linux BASE_BAUD define should match this configuration.
 177  *    baseBaud = cpuClock/(uartDivisor*16)
 178  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 179  * set Linux BASE_BAUD to 403200.
 180  */
 181 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* external serial clock */
 182 #undef  CONFIG_SYS_405_UART_ERRATA_59          /* 405GP/CR Rev. D silicon */
 183 #define CONFIG_SYS_BASE_BAUD        691200
 184
 185 /* The following table includes the supported baudrates */
 186 #define CONFIG_SYS_BAUDRATE_TABLE  \
 187     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 188
 189 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 190 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 191
 192 #define CONFIG_SYS_I2C
 193 #define CONFIG_SYS_I2C_PPC4XX
 194 #define CONFIG_SYS_I2C_PPC4XX_CH0
 195 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 196 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 197
 198
 199 /*-----------------------------------------------------------------------
 200  * PCI stuff
 201  *-----------------------------------------------------------------------
 202  */
 203 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 204 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 205 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 206
 207 #define CONFIG_PCI                      /* include pci support          */
 208 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 209 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 210 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 211                                         /* resource configuration       */
 212
 213 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000   /* PCI Vendor ID: to-do!!!      */
 214 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000   /* PCI Device ID: to-do!!!      */
 215 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 216 #define CONFIG_SYS_PCI_PTM1MS   0x80000001      /* 2GB, enable hard-wired to 1  */
 217 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 218 #define CONFIG_SYS_PCI_PTM2LA   0x00000000      /* disabled                     */
 219 #define CONFIG_SYS_PCI_PTM2MS   0x00000000      /* disabled                     */
 220 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 221
 222 /*-----------------------------------------------------------------------
 223  * External peripheral base address
 224  *-----------------------------------------------------------------------
 225  */
 226 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 227 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 228
 229 #define CONFIG_SYS_KEY_REG_BASE_ADDR    0xF0100000
 230 #define CONFIG_SYS_IR_REG_BASE_ADDR     0xF0200000
 231 #define CONFIG_SYS_FPGA_REG_BASE_ADDR   0xF0300000
 232
 233 /*-----------------------------------------------------------------------
 234  * Start addresses for the final memory configuration
 235  * (Set up by the startup code)
 236  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 237  */
 238 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 239 #define CONFIG_SYS_FLASH_BASE           0xFFF80000
 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 241 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 242 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 243
 244 /*
 245  * For booting Linux, the board info and command line data
 246  * have to be in the first 8 MB of memory, since this is
 247  * the maximum mapped by the Linux kernel during initialization.
 248  */
 249 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 250
 251 /*-----------------------------------------------------------------------
 252  * FLASH organization
 253  */
 254 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 255 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 256
 257 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 258 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 259
 260 /*
 261  * Init Memory Controller:
 262  *
 263  * BR0/1 and OR0/1 (FLASH)
 264  */
 265
 266 #define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0        */
 267 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 268
 269
 270 /* Configuration Port location */
 271 #define CONFIG_PORT_ADDR        0xF0000500
 272
 273 #if defined(CONFIG_CMD_KGDB)
 274 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 275 #endif
 276 #endif  /* __CONFIG_H */