include/configs/KAREF.h

   1 /*
   2  * (C) Copyright 2004 Sandburst Corporation
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /************************************************************************
  24  * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
  25  *                  design.
  26  ***********************************************************************/
  27
  28 /*
  29  * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
  30  *
  31  */
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /*-----------------------------------------------------------------------
  37  * High Level Configuration Options
  38  *----------------------------------------------------------------------*/
  39 #define CONFIG_KAREF         1          /* Board is Kamino Ref Variant */
  40 #define CONFIG_440GX              1          /* Specifc GX support      */
  41 #define CONFIG_440                1          /* ... PPC440 family       */
  42 #define CONFIG_4xx                1          /* ... PPC4xx family       */
  43 #define CONFIG_BOARD_EARLY_INIT_F 1          /* Call board_pre_init     */
  44 #define CONFIG_MISC_INIT_F        1          /* Call board misc_init_f  */
  45 #define CONFIG_MISC_INIT_R        1          /* Call board misc_init_r  */
  46 #undef  CONFIG_SYS_DRAM_TEST                         /* Disable-takes long time!*/
  47 #define CONFIG_SYS_CLK_FREQ       66666666   /* external freq to pll    */
  48
  49 #define CONFIG_VERY_BIG_RAM 1
  50 #define CONFIG_VERSION_VARIABLE
  51
  52 #define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
  53
  54 /*-----------------------------------------------------------------------
  55  * Base addresses -- Note these are effective addresses where the
  56  * actual resources get mapped (not physical addresses)
  57  *----------------------------------------------------------------------*/
  58 #define CONFIG_SYS_SDRAM_BASE          0x00000000    /* _must_ be 0             */
  59 #define CONFIG_SYS_FLASH_BASE          0xfff80000    /* start of FLASH          */
  60 #define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor */
  61 #define CONFIG_SYS_PCI_MEMBASE         0x80000000    /* mapped pci memory       */
  62 #define CONFIG_SYS_PERIPHERAL_BASE    0xe0000000    /* internal peripherals     */
  63 #define CONFIG_SYS_ISRAM_BASE          0xc0000000    /* internal SRAM           */
  64 #define CONFIG_SYS_PCI_BASE            0xd0000000    /* internal PCI regs       */
  65
  66 #define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
  67 #define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
  68 #define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
  69 #define CONFIG_SYS_BME32_BASE         (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
  70 #define CONFIG_SYS_GPIO_BASE          (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
  71
  72 /* Here for completeness */
  73 #define CONFIG_SYS_OFEMAC_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
  74
  75 /*-----------------------------------------------------------------------
  76  * Initial RAM & stack pointer (placed in internal SRAM)
  77  *----------------------------------------------------------------------*/
  78 #define CONFIG_SYS_TEMP_STACK_OCM    1
  79 #define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
  80 #define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address       */
  81 #define CONFIG_SYS_INIT_RAM_END      0x2000          /* End of used area in RAM */
  82 #define CONFIG_SYS_GBL_DATA_SIZE     128             /* num bytes initial data  */
  83
  84 #define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  85 #define CONFIG_SYS_POST_WORD_ADDR    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  86 #define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_POST_WORD_ADDR
  87
  88 #define CONFIG_SYS_MONITOR_LEN        (256 * 1024)   /* Rsrv 256kB for Mon      */
  89 #define CONFIG_SYS_MALLOC_LEN         (128 * 1024)   /* Rsrv 128kB for malloc   */
  90
  91 /*-----------------------------------------------------------------------
  92  * Serial Port
  93  *----------------------------------------------------------------------*/
  94 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
  95 #define CONFIG_SERIAL_MULTI   1
  96 #define CONFIG_BAUDRATE       9600
  97
  98 #define CONFIG_SYS_BAUDRATE_TABLE  \
  99     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 100
 101 /*-----------------------------------------------------------------------
 102  * NVRAM/RTC
 103  *
 104  * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 105  * The DS1743 code assumes this condition (i.e. -- it assumes the base
 106  * address for the RTC registers is:
 107  *
 108  *      CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
 109  *
 110  *----------------------------------------------------------------------*/
 111 #define CONFIG_SYS_NVRAM_SIZE         (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
 112 #define CONFIG_RTC_DS174x     1              /* DS1743 RTC              */
 113
 114 /*-----------------------------------------------------------------------
 115  * FLASH related
 116  *----------------------------------------------------------------------*/
 117 #define CONFIG_SYS_MAX_FLASH_BANKS   1               /* number of banks         */
 118 #define CONFIG_SYS_MAX_FLASH_SECT    8               /* sectors per device      */
 119
 120 #undef  CONFIG_SYS_FLASH_CHECKSUM
 121 #define CONFIG_SYS_FLASH_ERASE_TOUT  120000          /* Flash Erase TO (in ms)   */
 122 #define CONFIG_SYS_FLASH_WRITE_TOUT  500             /* Flash Write TO(in ms)    */
 123
 124 /*-----------------------------------------------------------------------
 125  * DDR SDRAM
 126  *----------------------------------------------------------------------*/
 127 #define CONFIG_SPD_EEPROM     1              /* Use SPD EEPROM for setup*/
 128 #define SPD_EEPROM_ADDRESS    {0x53}         /* SPD i2c spd addresses   */
 129
 130 /*-----------------------------------------------------------------------
 131  * I2C
 132  *----------------------------------------------------------------------*/
 133 #define CONFIG_HARD_I2C       1              /* I2C hardware support    */
 134 #undef  CONFIG_SOFT_I2C                      /* I2C !bit-banged         */
 135 #define CONFIG_SYS_I2C_SPEED          400000         /* I2C speed 400kHz        */
 136 #define CONFIG_SYS_I2C_SLAVE          0x7F           /* I2C slave address       */
 137 #define CONFIG_SYS_I2C_NOPROBES      {0x69}          /* Don't probe these addrs */
 138 #define CONFIG_I2C_BUS1       1              /* Include i2c bus 1 supp  */
 139
 140
 141 /*-----------------------------------------------------------------------
 142  * Environment
 143  *----------------------------------------------------------------------*/
 144 #define CONFIG_ENV_IS_IN_NVRAM   1                   /* Environment uses NVRAM  */
 145 #undef  CONFIG_ENV_IS_IN_FLASH               /* ... not in flash        */
 146 #undef  CONFIG_ENV_IS_IN_EEPROM              /* ... not in EEPROM       */
 147 #define CONFIG_ENV_OVERWRITE  1              /* allow env overwrite     */
 148
 149 #define CONFIG_ENV_SIZE       0x1000         /* Size of Env vars        */
 150 #define CONFIG_ENV_ADDR       (CONFIG_SYS_NVRAM_BASE_ADDR)
 151
 152 #define CONFIG_BOOTDELAY      5             /* 5 second autoboot */
 153
 154 #define CONFIG_LOADS_ECHO     1              /* echo on for serial dnld */
 155 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1               /* allow baudrate change   */
 156
 157 /*-----------------------------------------------------------------------
 158  * Networking
 159  *----------------------------------------------------------------------*/
 160 #define CONFIG_PPC4xx_EMAC
 161 #define CONFIG_MII            1              /* MII PHY management      */
 162 #define CONFIG_NET_MULTI      1
 163 #define CONFIG_PHY_ADDR       0xff           /* no phy on EMAC0         */
 164 #define CONFIG_PHY1_ADDR      0xff           /* no phy on EMAC1         */
 165 #define CONFIG_PHY2_ADDR      0x08           /* PHY addr, MGMT, EMAC2   */
 166 #define CONFIG_PHY3_ADDR      0x18           /* PHY addr, LCL, EMAC3    */
 167 #define CONFIG_HAS_ETH0
 168 #define CONFIG_HAS_ETH1
 169 #define CONFIG_HAS_ETH2
 170 #define CONFIG_HAS_ETH3
 171 #define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
 172 #define CONFIG_CIS8201_PHY    1              /* RGMII mode for Cicada   */
 173 #define CONFIG_CIS8201_SHORT_ETCH 1          /* Use short etch mode     */
 174 #define CONFIG_PHY_GIGE       1              /* GbE speed/duplex detect */
 175 #define CONFIG_PHY_RESET_DELAY 1000
 176 #define CONFIG_NETMASK        255.255.0.0
 177 #define CONFIG_ETHADDR        00:00:00:00:00:00 /* No EMAC 0 support    */
 178 #define CONFIG_ETH1ADDR       00:00:00:00:00:00 /* No EMAC 1 support    */
 179 #define CONFIG_SYS_RX_ETH_BUFFER     32      /* #eth rx buff & descrs   */
 180
 181
 182 /*
 183  * BOOTP options
 184  */
 185 #define CONFIG_BOOTP_BOOTFILESIZE
 186 #define CONFIG_BOOTP_BOOTPATH
 187 #define CONFIG_BOOTP_GATEWAY
 188 #define CONFIG_BOOTP_HOSTNAME
 189
 190
 191 /*
 192  * Command line configuration.
 193  */
 194 #include <config_cmd_default.h>
 195
 196 #define CONFIG_CMD_PCI
 197 #define CONFIG_CMD_IRQ
 198 #define CONFIG_CMD_I2C
 199 #define CONFIG_CMD_DHCP
 200 #define CONFIG_CMD_DATE
 201 #define CONFIG_CMD_BEDBUG
 202 #define CONFIG_CMD_PING
 203 #define CONFIG_CMD_DIAG
 204 #define CONFIG_CMD_MII
 205 #define CONFIG_CMD_NET
 206 #define CONFIG_CMD_ELF
 207 #define CONFIG_CMD_IDE
 208 #define CONFIG_CMD_FAT
 209
 210
 211 /* Include NetConsole support */
 212 #define CONFIG_NETCONSOLE
 213
 214 /* Include auto complete with tabs */
 215 #define CONFIG_AUTO_COMPLETE 1
 216 #define CONFIG_SYS_ALT_MEMTEST       1       /* use real memory test     */
 217
 218 #define CONFIG_SYS_LONGHELP                          /* undef to save memory    */
 219 #define CONFIG_SYS_PROMPT             "KaRefDes=> "  /* Monitor Command Prompt  */
 220
 221 #define CONFIG_SYS_HUSH_PARSER         1             /* HUSH for ext'd cli      */
 222 #define CONFIG_SYS_PROMPT_HUSH_PS2    "> "
 223
 224
 225 /*-----------------------------------------------------------------------
 226  * Console Buffer
 227  *----------------------------------------------------------------------*/
 228 #if defined(CONFIG_CMD_KGDB)
 229 #define CONFIG_SYS_CBSIZE             1024           /* Console I/O Buffer Size */
 230 #else
 231 #define CONFIG_SYS_CBSIZE             256            /* Console I/O Buffer Size */
 232 #endif
 233 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 234                                              /* Print Buffer Size       */
 235 #define CONFIG_SYS_MAXARGS            16             /* max number of cmd args  */
 236 #define CONFIG_SYS_BARGSIZE           CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size     */
 237
 238 /*-----------------------------------------------------------------------
 239  * Memory Test
 240  *----------------------------------------------------------------------*/
 241 #define CONFIG_SYS_MEMTEST_START     0x0400000       /* memtest works on        */
 242 #define CONFIG_SYS_MEMTEST_END        0x0C00000      /* 4 ... 12 MB in DRAM     */
 243
 244 /*-----------------------------------------------------------------------
 245  * Compact Flash (in true IDE mode)
 246  *----------------------------------------------------------------------*/
 247 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 248 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 249
 250 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 251 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE busses    */
 252 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 253
 254 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0000000
 255 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 256 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000   /* Offset for data I/O */
 257 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000   /* Offset for normal register accesses*/
 258 #define CONFIG_SYS_ATA_ALT_OFFSET       0x100000 /* Offset for alternate registers */
 259
 260 #define CONFIG_SYS_ATA_STRIDE           2        /* Directly connected CF, needs a stride
 261                                             to get to the correct offset */
 262 #define CONFIG_DOS_PARTITION  1              /* Include dos partition   */
 263
 264 /*-----------------------------------------------------------------------
 265  * PCI
 266  *----------------------------------------------------------------------*/
 267 /* General PCI */
 268 #define CONFIG_PCI                           /* include pci support     */
 269 #define CONFIG_PCI_PNP                       /* do pci plug-and-play    */
 270 #define CONFIG_PCI_SCAN_SHOW                 /* show pci devices        */
 271 #define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
 272
 273 /* Board-specific PCI */
 274 #define CONFIG_SYS_PCI_TARGET_INIT                   /* let board init pci target*/
 275
 276 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA        /* Sandburst */
 277 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe        /* Whatever */
 278
 279 /*
 280  * For booting Linux, the board info and command line data
 281  * have to be in the first 8 MB of memory, since this is
 282  * the maximum mapped by the Linux kernel during initialization.
 283  */
 284 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 285
 286 /*
 287  * Internal Definitions
 288  *
 289  * Boot Flags
 290  */
 291 #define BOOTFLAG_COLD         0x01           /* Normal PowerOn: Boot from FLASH */
 292 #define BOOTFLAG_WARM         0x02           /* Software reboot */
 293
 294 #if defined(CONFIG_CMD_KGDB)
 295 #define CONFIG_KGDB_BAUDRATE  230400         /* kgdb serial port baud   */
 296 #define CONFIG_KGDB_SER_INDEX 2              /* kgdb serial port        */
 297 #endif
 298
 299 /*-----------------------------------------------------------------------
 300  * Miscellaneous configurable options
 301  *----------------------------------------------------------------------*/
 302 #undef CONFIG_WATCHDOG                       /* watchdog disabled       */
 303 #define CONFIG_SYS_LOAD_ADDR          0x8000000      /* default load address    */
 304 #define CONFIG_SYS_EXTBDINFO          1              /* use extended board_info */
 305
 306 #define CONFIG_SYS_HZ                 100            /* decr freq: 1 ms ticks   */
 307
 308
 309 #endif  /* __CONFIG_H */