include/configs/KUP4K.h

   1 /*
   2   * (C) Copyright 2000-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  * Derived from ../tqm8xx/tqm8xx.c
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  39 #define CONFIG_KUP4K            1       /* ...on a KUP4K module */
  40
  41 #define CONFIG_SYS_TEXT_BASE    0x40000000
  42
  43 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  44 #undef  CONFIG_8xx_CONS_SMC2
  45 #undef  CONFIG_8xx_CONS_NONE
  46 #define CONFIG_BAUDRATE         115200  /* console baudrate             */
  47 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  48
  49 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  50
  51 #undef  CONFIG_BOOTARGS
  52
  53 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
  54 "slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;"                            \
  55  "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0"            \
  56 "slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;"                            \
  57  "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0"            \
  58 "nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0"     \
  59 "fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw;          \
  60  bootm 400000 \0"                                                               \
  61 "panic_boot=echo No Bootdevice !!! reset\0"                                     \
  62 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0"                \
  63 "ramargs=setenv bootargs root=/dev/ram rw\0"                                    \
  64 "addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}"                  \
  65  ":${netmask}:${hostname}:${netdev}:off\0"                                      \
  66 "addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug}      \
  67  hw=${hw} key1=${key1} panic=1 mem=${mem}\0"                                    \
  68 "console=ttyCPM0,115200\0"                                                      \
  69 "netdev=eth0\0"                                                                 \
  70 "contrast=20\0"                                                                 \
  71 "silent=1\0"                                                                    \
  72 "mtdparts=" MTDPARTS_DEFAULT "\0"                                               \
  73 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"         \
  74 "update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};"          \
  75  "cp.b 200000 40050000 14000\0"
  76
  77 #define CONFIG_BOOTCOMMAND  \
  78     "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
  79
  80 #define CONFIG_PREBOOT  "setenv preboot; saveenv"
  81
  82 #define CONFIG_MISC_INIT_R      1
  83 #define CONFIG_MISC_INIT_F      1
  84
  85 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  86 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE    /* don't allow baudrate change  */
  87
  88 #define CONFIG_WATCHDOG 1               /* watchdog enabled             */
  89
  90 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  91
  92 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  93
  94 /*
  95  * BOOTP options
  96  */
  97 #define CONFIG_BOOTP_SUBNETMASK
  98 #define CONFIG_BOOTP_GATEWAY
  99 #define CONFIG_BOOTP_HOSTNAME
 100 #define CONFIG_BOOTP_BOOTPATH
 101 #define CONFIG_BOOTP_BOOTFILESIZE
 102
 103 #define CONFIG_MAC_PARTITION
 104 #define CONFIG_DOS_PARTITION
 105
 106 /*
 107  * enable I2C and select the hardware/software driver
 108  */
 109 #define CONFIG_SYS_I2C
 110 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 111 #define CONFIG_SYS_I2C_SOFT_SPEED       93000   /* 93 kHz is supposed to work */
 112 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 113
 114 /*
 115  * Software (bit-bang) I2C driver configuration
 116  */
 117 #define PB_SCL          0x00000020      /* PB 26 */
 118 #define PB_SDA          0x00000010      /* PB 27 */
 119
 120 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 121 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 122 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 123 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 124 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 125                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 126 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 127                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 128 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 129
 130 /*-----------------------------------------------------------------------
 131  * I2C Configuration
 132  */
 133
 134 #define CONFIG_SYS_I2C_PICIO_ADDR       0x21    /* PCF8574 IO Expander */
 135 #define CONFIG_SYS_I2C_RTC_ADDR         0x51    /* PCF8563 RTC */
 136
 137 /* List of I2C addresses to be verified by POST */
 138
 139 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_PICIO_ADDR,     \
 140                                          CONFIG_SYS_I2C_RTC_ADDR,       \
 141                                         }
 142
 143 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 144
 145 #define CONFIG_SYS_DISCOVER_PHY
 146 #define CONFIG_MII
 147
 148 /* Define to allow the user to overwrite serial and ethaddr */
 149 #define CONFIG_ENV_OVERWRITE
 150
 151 /*
 152  * Command line configuration.
 153  */
 154 #include <config_cmd_default.h>
 155
 156 #define CONFIG_CMD_DATE
 157 #define CONFIG_CMD_DHCP
 158 #define CONFIG_CMD_I2C
 159 #define CONFIG_CMD_IDE
 160 #define CONFIG_CMD_MII
 161 #define CONFIG_CMD_NFS
 162 #define CONFIG_CMD_FAT
 163 #define CONFIG_CMD_SNTP
 164
 165 #ifdef CONFIG_POST
 166     #define CONFIG_CMD_DIAG
 167 #endif
 168
 169 /*
 170  * Miscellaneous configurable options
 171  */
 172 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 173 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 174 #if defined(CONFIG_CMD_KGDB)
 175 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 176 #else
 177 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size      */
 178 #endif
 179 /* Print Buffer Size */
 180 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 181 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 182 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 183
 184 #define CONFIG_SYS_MEMTEST_START        0x000400000     /* memtest works on     */
 185 #define CONFIG_SYS_MEMTEST_END          0x005C00000     /* 4 ... 92 MB in DRAM  */
 186 #define CONFIG_SYS_ALT_MEMTEST 1
 187 #define CONFIG_SYS_MEMTEST_SCRATCH      0x90000200      /* using latch as scratch register */
 188
 189 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 190
 191 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 192
 193 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 115200 }
 194
 195 #define CONFIG_SYS_CONSOLE_INFO_QUIET 1
 196
 197 /*
 198  * Low Level Configuration Settings
 199  * (address mappings, register initial values, etc.)
 200  * You should know what you are doing if you make changes here.
 201  */
 202 /*-----------------------------------------------------------------------
 203  * Internal Memory Mapped Register
 204  */
 205 #define CONFIG_SYS_IMMR         0xFFF00000
 206
 207 /*-----------------------------------------------------------------------
 208  * Definitions for initial stack pointer and data area (in DPRAM)
 209  */
 210 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 211 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 212 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 213 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 214
 215 /*-----------------------------------------------------------------------
 216  * Start addresses for the final memory configuration
 217  * (Set up by the startup code)
 218  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 219  */
 220 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 221 #define CONFIG_SYS_FLASH_BASE           0x40000000
 222 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 224 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 225
 226 /*
 227  * For booting Linux, the board info and command line data
 228  * have to be in the first 8 MB of memory, since this is
 229  * the maximum mapped by the Linux kernel during initialization.
 230  */
 231 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 232
 233 /*-----------------------------------------------------------------------
 234  * FLASH organization
 235  */
 236 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 237 #define CONFIG_SYS_MAX_FLASH_SECT       19      /* max number of sectors on one chip    */
 238
 239 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 240 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 241
 242 #define CONFIG_ENV_IS_IN_FLASH  1
 243 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 244 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector     */
 245 #define CONFIG_ENV_SECT_SIZE    0x10000
 246
 247 /*-----------------------------------------------------------------------
 248  * Dynamic MTD partition support
 249  */
 250 #define MTDPARTS_DEFAULT        "mtdparts=40000000.flash:256k(u-boot)," \
 251                                                 "64k(env),"             \
 252                                                 "128k(splash),"         \
 253                                                 "512k(etc),"            \
 254                                                 "64k(hw-info)"
 255
 256 /*-----------------------------------------------------------------------
 257  * Hardware Information Block
 258  */
 259 #define CONFIG_SYS_HWINFO_OFFSET        0x000F0000      /* offset of HW Info block */
 260 #define CONFIG_SYS_HWINFO_SIZE          0x00000100      /* size   of HW Info block */
 261 #define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D              /* 'K&P<CR>' */
 262
 263 /*-----------------------------------------------------------------------
 264  * Cache Configuration
 265  */
 266 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 267 #if defined(CONFIG_CMD_KGDB)
 268 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 269 #endif
 270
 271 /*-----------------------------------------------------------------------
 272  * SYPCR - System Protection Control                            11-9
 273  * SYPCR can only be written once after reset!
 274  *-----------------------------------------------------------------------
 275  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 276  */
 277 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 278
 279 /*-----------------------------------------------------------------------
 280  * SIUMCR - SIU Module Configuration                            11-6
 281  *-----------------------------------------------------------------------
 282  * PCMCIA config., multi-function pin tri-state
 283  */
 284 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
 285
 286 /*-----------------------------------------------------------------------
 287  * TBSCR - Time Base Status and Control                         11-26
 288  *-----------------------------------------------------------------------
 289  * Clear Reference Interrupt Status, Timebase freezing enabled
 290  */
 291 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 292
 293 /*-----------------------------------------------------------------------
 294  * RTCSC - Real-Time Clock Status and Control Register          11-27
 295  *-----------------------------------------------------------------------
 296  */
 297 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 298
 299 /*-----------------------------------------------------------------------
 300  * PISCR - Periodic Interrupt Status and Control                11-31
 301  *-----------------------------------------------------------------------
 302  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 303  */
 304 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 305
 306 /*-----------------------------------------------------------------------
 307  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 308  *-----------------------------------------------------------------------
 309  * Reset PLL lock status sticky bit, timer expired status bit and timer
 310  * interrupt status bit
 311  *
 312  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 313  */
 314 #define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 315
 316 /*-----------------------------------------------------------------------
 317  * SCCR - System Clock and reset Control Register               15-27
 318  *-----------------------------------------------------------------------
 319  * Set clock output, timebase and RTC source and divider,
 320  * power management and some other internal clocks
 321  */
 322 #define SCCR_MASK       SCCR_EBDF00
 323 #define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 |  \
 324                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 325                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 326                          SCCR_DFALCD00)
 327
 328 /*-----------------------------------------------------------------------
 329  * PCMCIA stuff
 330  *-----------------------------------------------------------------------
 331  *
 332  */
 333
 334 /* KUP4K use both slots, SLOT_A as "primary". */
 335 #define CONFIG_PCMCIA_SLOT_A 1
 336
 337 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 338 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 339 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 340 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 341 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 342 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 343 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 344 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 345
 346 #define PCMCIA_SOCKETS_NO 2
 347 #define PCMCIA_MEM_WIN_NO 8
 348 /*-----------------------------------------------------------------------
 349  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 350  *-----------------------------------------------------------------------
 351  */
 352
 353 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 354 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 355
 356 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 357 #define CONFIG_IDE_LED          1       /* LED   for ide supported      */
 358 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 359
 360 #define CONFIG_SYS_IDE_MAXBUS           2
 361 #define CONFIG_SYS_IDE_MAXDEVICE        4
 362
 363 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 364
 365 #define CONFIG_SYS_ATA_IDE1_OFFSET      (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
 366
 367 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 368
 369 /* Offset for data I/O                  */
 370 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 371
 372 /* Offset for normal register accesses  */
 373 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 374
 375 /* Offset for alternate registers       */
 376 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 377
 378 /*-----------------------------------------------------------------------
 379  *
 380  *-----------------------------------------------------------------------
 381  *
 382  */
 383 #define CONFIG_SYS_DER 0
 384
 385 /*
 386  * Init Memory Controller:
 387  *
 388  * BR0/1 and OR0/1 (FLASH)
 389  */
 390 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 391
 392 /* used to re-map FLASH both when starting from SRAM or FLASH:
 393  * restrict access enough to keep SRAM working (if any)
 394  * but not too much to meddle with FLASH accesses
 395  */
 396 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 397 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 398
 399 /*
 400  * FLASH timing:
 401  */
 402 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV2  | OR_CSNT_SAM | \
 403                                  OR_SCY_5_CLK | OR_EHTR | OR_BI)
 404
 405 #define CONFIG_SYS_OR0_REMAP \
 406         (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 407 #define CONFIG_SYS_OR0_PRELIM \
 408         (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 409 #define CONFIG_SYS_BR0_PRELIM \
 410         ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 411
 412
 413 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 414 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 415
 416 /*
 417  * Memory Periodic Timer Prescaler
 418  *
 419  * The Divider for PTA (refresh timer) configuration is based on an
 420  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 421  * the number of chip selects (NCS) and the actually needed refresh
 422  * rate is done by setting MPTPR.
 423  *
 424  * PTA is calculated from
 425  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 426  *
 427  *      gclk      CPU clock (not bus clock!)
 428  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 429  *
 430  * 4096  Rows from SDRAM example configuration
 431  * 1000  factor s -> ms
 432  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 433  *    4  Number of refresh cycles per period
 434  *   64  Refresh cycle in ms per number of rows
 435  * --------------------------------------------
 436  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 437  *
 438  * 50 MHz => 50.000.000 / Divider =  98
 439  * 66 Mhz => 66.000.000 / Divider = 129
 440  * 80 Mhz => 80.000.000 / Divider = 156
 441  */
 442 #if   defined(CONFIG_80MHz)
 443 #define CONFIG_SYS_MAMR_PTA             156
 444 #elif defined(CONFIG_66MHz)
 445 #define CONFIG_SYS_MAMR_PTA             129
 446 #else           /*   50 MHz */
 447 #define CONFIG_SYS_MAMR_PTA              98
 448 #endif  /*CONFIG_??MHz */
 449
 450 /*
 451  * For 16 MBit, refresh rates could be 31.3 us
 452  * (= 64 ms / 2K = 125 / quad bursts).
 453  * For a simpler initialization, 15.6 us is used instead.
 454  *
 455  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 456  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 457  */
 458 #define CONFIG_SYS_MPTPR 0x400
 459
 460 /*
 461  * MAMR settings for SDRAM
 462  */
 463
 464 /* 8 column SDRAM */
 465 #define CONFIG_SYS_MAMR_8COL 0x68802114
 466 /* 9 column SDRAM */
 467 #define CONFIG_SYS_MAMR_9COL 0x68904114
 468
 469 /*
 470  * Chip Selects
 471  */
 472 #define CONFIG_SYS_OR0
 473 #define CONFIG_SYS_BR0
 474
 475 #define CONFIG_SYS_OR1_8COL 0xFF000A00
 476 #define CONFIG_SYS_BR1_8COL 0x00000081
 477 #define CONFIG_SYS_OR2_8COL 0xFE000A00
 478 #define CONFIG_SYS_BR2_8COL 0x01000081
 479 #define CONFIG_SYS_OR3_8COL 0xFC000A00
 480 #define CONFIG_SYS_BR3_8COL 0x02000081
 481
 482 #define CONFIG_SYS_OR1_9COL 0xFE000A00
 483 #define CONFIG_SYS_BR1_9COL 0x00000081
 484 #define CONFIG_SYS_OR2_9COL 0xFE000A00
 485 #define CONFIG_SYS_BR2_9COL 0x02000081
 486 #define CONFIG_SYS_OR3_9COL 0xFE000A00
 487 #define CONFIG_SYS_BR3_9COL 0x04000081
 488
 489 #define CONFIG_SYS_OR4 0xFFFF8926
 490 #define CONFIG_SYS_BR4 0x90000401
 491
 492 #define CONFIG_SYS_OR5 0xFFC007F0  /* EPSON: 4 MB  17 WS or externel TA */
 493 #define CONFIG_SYS_BR5 0x80080801  /* Start at 0x80080000 */
 494
 495 #define LATCH_ADDR 0x90000200
 496
 497 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
 498 #define CONFIG_AUTOBOOT_STOP_STR        "."
 499 #define CONFIG_SILENT_CONSOLE           1
 500 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* enble null device            */
 501 #define CONFIG_VERSION_VARIABLE         1
 502
 503 /* pass open firmware flat tree */
 504 #define CONFIG_OF_LIBFDT        1
 505 #define CONFIG_OF_BOARD_SETUP   1
 506
 507 #endif  /* __CONFIG_H */