include/configs/KUP4X.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  * Derived from ../tqm8xx/tqm8xx.c
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC859T          1       /* This is a MPC859T CPU                */
  39 #define CONFIG_KUP4X            1       /* ...on a KUP4X module                 */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1                   */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate                     */
  45 #if 0
  46 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled                    */
  47 #else
  48 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second              */
  49 #endif
  50
  51 #define CONFIG_BOARD_TYPES      1       /* support board types                  */
  52
  53 #define CFG_8XX_FACT            8       /* Multiply by 8                        */
  54 #define CFG_8XX_XIN             16000000        /* 16 MHz in                    */
  55
  56
  57 #define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
  58
  59 /* should ALWAYS define this, measure_gclk in speed.c is unreliable */
  60 /* in general, we always know this for FADS+new ADS anyway */
  61 #define CONFIG_8xx_GCLK_FREQ     MPC8XX_HZ
  62
  63
  64 #undef  CONFIG_BOOTARGS
  65
  66
  67 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
  68 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"                            \
  69   "run addhw;diskboot 200000 0:1;bootm 200000\0"                                \
  70 "usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
  71  run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
  72  usb stop; bootm 200000\0"      \
  73 "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"                          \
  74 "panic_boot=echo No Bootdevice !!! reset\0"                                     \
  75 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"    \
  76 "ramargs=setenv bootargs root=/dev/ram rw\0"                                    \
  77 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)"       \
  78  ":$(netmask):$(hostname):$(netdev):off\0"                                      \
  79 "addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0"             \
  80 "netdev=eth0\0"                                                                 \
  81 "silent=1\0"                                                                    \
  82 "load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0"         \
  83 "update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);"          \
  84  "cp.b 200000 40040000 14000\0"
  85
  86 #define CONFIG_BOOTCOMMAND  \
  87     "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
  88
  89
  90 #define CONFIG_MISC_INIT_R      1
  91 #define CONFIG_MISC_INIT_F      1
  92
  93 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  94 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  95
  96 #define CONFIG_WATCHDOG         1       /* watchdog enabled             */
  97
  98 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  99
 100 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 101
 102 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 103
 104 #define CONFIG_MAC_PARTITION
 105 #define CONFIG_DOS_PARTITION
 106
 107 /*
 108  * enable I2C and select the hardware/software driver
 109  */
 110 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 111 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 112
 113 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 114 #define CFG_I2C_SLAVE           0xFE
 115
 116 #ifdef CONFIG_SOFT_I2C
 117 /*
 118  * Software (bit-bang) I2C driver configuration
 119  */
 120 #define PB_SCL          0x00000020      /* PB 26 */
 121 #define PB_SDA          0x00000010      /* PB 27 */
 122
 123 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 124 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 125 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 126 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 127 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 128                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 129 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 130                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 131 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 132 #endif  /* CONFIG_SOFT_I2C */
 133
 134
 135 /*-----------------------------------------------------------------------
 136  * I2C Configuration
 137  */
 138
 139 #define CFG_I2C_PICIO_ADDR      0x21    /* PCF8574 IO Expander                  */
 140 #define CFG_I2C_RTC_ADDR        0x51    /* PCF8563 RTC                          */
 141
 142
 143 /* List of I2C addresses to be verified by POST */
 144
 145 #define I2C_ADDR_LIST   {CFG_I2C_PICIO_ADDR,    \
 146                         CFG_I2C_RTC_ADDR,       \
 147                         }
 148
 149
 150 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 151
 152 #define CFG_DISCOVER_PHY
 153
 154 #if 0
 155 #define CONFIG_ETHADDR                  00:0B:64:80:00:00 /* our OUI from IEEE */
 156 #endif
 157 #undef CONFIG_KUP4K_LOGO
 158
 159 /* Define to allow the user to overwrite serial and ethaddr */
 160 #define CONFIG_ENV_OVERWRITE
 161
 162
 163 #if 1
 164 /* POST support */
 165
 166 #define CONFIG_POST             (CFG_POST_CPU      | \
 167                                  CFG_POST_RTC      | \
 168                                  CFG_POST_I2C)
 169
 170 #ifdef CONFIG_POST
 171 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 172 #else
 173 #define CFG_CMD_POST_DIAG 0
 174 #endif
 175 #endif
 176
 177 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 178                                 CFG_CMD_DATE    | \
 179                                 CFG_CMD_DHCP    | \
 180                                 CFG_CMD_FAT     | \
 181                                 CFG_CMD_I2C     | \
 182                                 CFG_CMD_IDE     | \
 183                                 CFG_CMD_NFS     | \
 184                                 CFG_CMD_POST_DIAG       | \
 185                                 CFG_CMD_SNTP    | \
 186                                 CFG_CMD_USB     )
 187
 188 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 189 #include <cmd_confdefs.h>
 190
 191 /*
 192  * Miscellaneous configurable options
 193  */
 194 #define CFG_LONGHELP                    /* undef to save memory         */
 195 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 196 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 197 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 198 #else
 199 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 200 #endif
 201 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 202 #define CFG_MAXARGS     16              /* max number of command args   */
 203 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 204
 205 #define CFG_MEMTEST_START       0x000400000     /* memtest works on     */
 206 #define CFG_MEMTEST_END         0x003C00000     /* 4 ... 60 MB in DRAM  */
 207 #define CFG_LOAD_ADDR           0x200000        /* default load address */
 208
 209 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 210
 211 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 115200 }
 212
 213 #define CFG_CONSOLE_INFO_QUIET 1
 214
 215 /*
 216  * Low Level Configuration Settings
 217  * (address mappings, register initial values, etc.)
 218  * You should know what you are doing if you make changes here.
 219  */
 220 /*-----------------------------------------------------------------------
 221  * Internal Memory Mapped Register
 222  */
 223 #define CFG_IMMR                0xFFF00000
 224
 225 /*-----------------------------------------------------------------------
 226  * Definitions for initial stack pointer and data area (in DPRAM)
 227  */
 228 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 229 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 230 #define CFG_GBL_DATA_SIZE       64      /* size in bytes reserved for initial data */
 231 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 232 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 233
 234 /*-----------------------------------------------------------------------
 235  * Start addresses for the final memory configuration
 236  * (Set up by the startup code)
 237  * Please note that CFG_SDRAM_BASE _must_ start at 0
 238  */
 239 #define CFG_SDRAM_BASE          0x00000000
 240 #define CFG_FLASH_BASE          0x40000000
 241 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 256 kB for Monitor   */
 242 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 243 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 244
 245 /*
 246  * For booting Linux, the board info and command line data
 247  * have to be in the first 8 MB of memory, since this is
 248  * the maximum mapped by the Linux kernel during initialization.
 249  */
 250 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 251
 252 /*-----------------------------------------------------------------------
 253  * FLASH organization
 254  */
 255 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 256 #define CFG_MAX_FLASH_SECT      19      /* max number of sectors on one chip    */
 257
 258 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 259 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 260
 261 #define CFG_ENV_IS_IN_FLASH     1
 262 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 263 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector     */
 264 #define CFG_ENV_SECT_SIZE       0x10000
 265
 266 /* Address and size of Redundant Environment Sector     */
 267 #if 0
 268 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 269 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 270 #endif
 271 /*-----------------------------------------------------------------------
 272  * Hardware Information Block
 273  */
 274 #if 1
 275 #define CFG_HWINFO_OFFSET       0x000F0000      /* offset of HW Info block */
 276 #define CFG_HWINFO_SIZE         0x00000100      /* size   of HW Info block */
 277 #define CFG_HWINFO_MAGIC        0x4B26500D      /* 'K&P<CR>' */
 278 #endif
 279 /*-----------------------------------------------------------------------
 280  * Cache Configuration
 281  */
 282 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 283 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 284 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 285 #endif
 286
 287 /*-----------------------------------------------------------------------
 288  * SYPCR - System Protection Control                            11-9
 289  * SYPCR can only be written once after reset!
 290  *-----------------------------------------------------------------------
 291  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 292  */
 293 #if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
 294 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 295                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 296 #else
 297 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 298 #endif
 299
 300 /*-----------------------------------------------------------------------
 301  * SIUMCR - SIU Module Configuration                            11-6
 302  *-----------------------------------------------------------------------
 303  * PCMCIA config., multi-function pin tri-state
 304  */
 305 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
 306
 307 /*-----------------------------------------------------------------------
 308  * TBSCR - Time Base Status and Control                         11-26
 309  *-----------------------------------------------------------------------
 310  * Clear Reference Interrupt Status, Timebase freezing enabled
 311  */
 312 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 313
 314
 315 /*-----------------------------------------------------------------------
 316  * PISCR - Periodic Interrupt Status and Control                11-31
 317  *-----------------------------------------------------------------------
 318  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 319  */
 320 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 321
 322
 323 /*-----------------------------------------------------------------------
 324  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 325  *-----------------------------------------------------------------------
 326  * set the PLL, the low-power modes and the reset control (15-29)
 327  */
 328 #define CFG_PLPRCR      ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) |   \
 329                                 PLPRCR_SPLSS | PLPRCR_TEXPS)
 330
 331
 332 /*-----------------------------------------------------------------------
 333  * SCCR - System Clock and reset Control Register               15-27
 334  *-----------------------------------------------------------------------
 335  * Set clock output, timebase and RTC source and divider,
 336  * power management and some other internal clocks
 337  */
 338 #define SCCR_MASK       SCCR_EBDF00
 339 #define CFG_SCCR        (SCCR_TBS | SCCR_EBDF01 |  \
 340                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 341                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 342                          SCCR_DFALCD00)
 343
 344 /*-----------------------------------------------------------------------
 345  * PCMCIA stuff
 346  *-----------------------------------------------------------------------
 347  *
 348  */
 349
 350 /* KUP4K use both slots, SLOT_A as "primary". */
 351 #define CONFIG_PCMCIA_SLOT_A 1
 352
 353 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 354 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 355 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 356 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 357 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 358 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 359 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 360 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 361
 362 #define PCMCIA_SOCKETS_NO 1
 363 #define PCMCIA_MEM_WIN_NO 8
 364 /*-----------------------------------------------------------------------
 365  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 366  *-----------------------------------------------------------------------
 367  */
 368
 369 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 370
 371 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 372 #define CONFIG_IDE_LED                  1   /* LED   for ide supported  */
 373 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 374
 375 #define CFG_IDE_MAXBUS          1
 376 #define CFG_IDE_MAXDEVICE       2
 377
 378 #define CFG_ATA_IDE0_OFFSET     0x0000
 379
 380 #define CFG_ATA_IDE1_OFFSET     (4 * CFG_PCMCIA_MEM_SIZE)
 381
 382 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 383
 384 /* Offset for data I/O                  */
 385 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 386
 387 /* Offset for normal register accesses  */
 388 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 389
 390 /* Offset for alternate registers       */
 391 #define CFG_ATA_ALT_OFFSET      0x0100
 392
 393
 394 /*-----------------------------------------------------------------------
 395  *
 396  *-----------------------------------------------------------------------
 397  *
 398  */
 399 #define CFG_DER 0
 400
 401 /*
 402  * Init Memory Controller:
 403  *
 404  * BR0/1 and OR0/1 (FLASH)
 405  */
 406 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 407
 408 /* used to re-map FLASH both when starting from SRAM or FLASH:
 409  * restrict access enough to keep SRAM working (if any)
 410  * but not too much to meddle with FLASH accesses
 411  */
 412 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 413 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 414
 415 /*
 416  * FLASH timing:
 417  */
 418 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 419                                  OR_SCY_2_CLK | OR_EHTR | OR_BI)
 420
 421 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 422 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 423 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 424
 425
 426 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 427 #define CFG_OR_TIMING_SDRAM     0x00000A00
 428
 429
 430 #define CFG_MPTPR 0x400
 431
 432 /*
 433  * MAMR settings for SDRAM
 434  */
 435 #define CFG_MAMR 0x80802114
 436
 437
 438 /*
 439  * Internal Definitions
 440  *
 441  * Boot Flags
 442  */
 443 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 444 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 445
 446
 447 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot     */
 448 #if 0
 449 #define CONFIG_AUTOBOOT_PROMPT          "Boote in %d Sekunden - stop mit \"2\"\n"
 450 #endif
 451 #define CONFIG_AUTOBOOT_STOP_STR        "."     /* easy to stop for now         */
 452 #define CONFIG_SILENT_CONSOLE   1
 453
 454 #define CONFIG_USB_STORAGE      1
 455 #define CONFIG_USB_SL811HS      1
 456
 457 #endif  /* __CONFIG_H */