include/configs/LANTEC.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * (C) Copyright 2001
   5  * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
   6  * Bruno Achauer, Exet AG, bruno@exet-ag.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  * [derived from config_TQM850L.h]
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /*
  36  * High Level Configuration Options
  37  * (easy to change)
  38  */
  39
  40 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  41 #define CONFIG_LANTEC           2       /* ...on a Lantec rev.2 board   */
  42
  43 #define CONFIG_SYS_TEXT_BASE    0x40000000
  44
  45 /*
  46  *  Port assignments (CONFIG_LANTEC == 1):
  47  *  - SMC1: J11 (MDB) ?
  48  *  - SMC2: J6  (Feature connector)
  49  *  - SCC2: J9  (RJ45)
  50  *  - SCC3: J8  (Sub-D9)
  51  *
  52  *  Port assignments (CONFIG_LANTEC == 2): TBD
  53  */
  54
  55
  56 #undef CONFIG_8xx_CONS_SMC2           /* Console is on SMC2           */
  57 #define CONFIG_8xx_CONS_SCC3
  58 #undef  CONFIG_8xx_CONS_NONE
  59 #define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps  */
  60 #if 0
  61 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  62 #else
  63 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  64 #endif
  65
  66 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  67
  68 #undef  CONFIG_BOOTARGS
  69 #define CONFIG_BOOTCOMMAND                                                      \
  70         "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000"
  71
  72 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  73 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  78
  79 /*
  80  * BOOTP options
  81  */
  82 #define CONFIG_BOOTP_SUBNETMASK
  83 #define CONFIG_BOOTP_GATEWAY
  84 #define CONFIG_BOOTP_HOSTNAME
  85 #define CONFIG_BOOTP_BOOTPATH
  86 #define CONFIG_BOOTP_BOOTFILESIZE
  87
  88
  89 /*
  90  * Command line configuration.
  91  */
  92 #include <config_cmd_default.h>
  93
  94 #define CONFIG_CMD_ASKENV
  95 #define CONFIG_CMD_CACHE
  96 #define CONFIG_CMD_CDP
  97 #define CONFIG_CMD_DATE
  98 #define CONFIG_CMD_DHCP
  99 #define CONFIG_CMD_DIAG
 100 #define CONFIG_CMD_FAT
 101 #define CONFIG_CMD_IMMAP
 102 #define CONFIG_CMD_PING
 103 #define CONFIG_CMD_PORTIO
 104 #define CONFIG_CMD_REGINFO
 105 #define CONFIG_CMD_SAVES
 106 #define CONFIG_CMD_SDRAM
 107 #define CONFIG_CMD_SNTP
 108
 109 #undef CONFIG_CMD_XIMG
 110
 111 #if !(CONFIG_LANTEC >= 2)
 112     #undef CONFIG_CMD_DATE
 113     #undef CONFIG_CMD_NET
 114 #endif
 115
 116
 117 #if CONFIG_LANTEC >= 2
 118 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 119 #endif
 120
 121 /*
 122  * Miscellaneous configurable options
 123  */
 124 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 125 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 126 #if defined(CONFIG_CMD_KGDB)
 127 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 128 #else
 129 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 130 #endif
 131 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 132 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 133 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 134
 135 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 136 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 137
 138 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 139
 140 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 141
 142 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 143
 144 /*
 145  * Low Level Configuration Settings
 146  * (address mappings, register initial values, etc.)
 147  * You should know what you are doing if you make changes here.
 148  */
 149 /*-----------------------------------------------------------------------
 150  * Internal Memory Mapped Register
 151  */
 152 #define CONFIG_SYS_IMMR         0xFFF00000
 153
 154 /*-----------------------------------------------------------------------
 155  * Definitions for initial stack pointer and data area (in DPRAM)
 156  */
 157 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 158 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 159 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 160 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 161
 162 /*-----------------------------------------------------------------------
 163  * Start addresses for the final memory configuration
 164  * (Set up by the startup code)
 165  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 166  */
 167 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 168 #define CONFIG_SYS_FLASH_BASE           0x40000000
 169 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 171 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 172
 173 /*
 174  * For booting Linux, the board info and command line data
 175  * have to be in the first 8 MB of memory, since this is
 176  * the maximum mapped by the Linux kernel during initialization.
 177  */
 178 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 179
 180 /*-----------------------------------------------------------------------
 181  * FLASH organization
 182  */
 183 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 184 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 185
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 188
 189 #define CONFIG_ENV_IS_IN_FLASH  1
 190 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 191 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 192
 193 /*-----------------------------------------------------------------------
 194  * Cache Configuration
 195  */
 196 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 197 #if defined(CONFIG_CMD_KGDB)
 198 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 199 #endif
 200
 201 /*-----------------------------------------------------------------------
 202  * SYPCR - System Protection Control                            11-9
 203  * SYPCR can only be written once after reset!
 204  *-----------------------------------------------------------------------
 205  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 206  */
 207 #if defined(CONFIG_WATCHDOG)
 208 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 209                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 210 #else
 211 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 212 #endif
 213
 214 /*-----------------------------------------------------------------------
 215  * SIUMCR - SIU Module Configuration                            11-6
 216  *-----------------------------------------------------------------------
 217  * PCMCIA config., multi-function pin tri-state
 218  */
 219 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK)
 220
 221 /*-----------------------------------------------------------------------
 222  * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX]
 223  *-----------------------------------------------------------------------
 224  */
 225 #define CONFIG_8xx_GCLK_FREQ    33000000
 226
 227 /*-----------------------------------------------------------------------
 228  * TBSCR - Time Base Status and Control                         11-26
 229  *-----------------------------------------------------------------------
 230  * Clear Reference Interrupt Status, Timebase freezing enabled
 231  */
 232 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 233
 234 /*-----------------------------------------------------------------------
 235  * RTCSC - Real-Time Clock Status and Control Register          11-27
 236  *-----------------------------------------------------------------------
 237  */
 238 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 239
 240 /*-----------------------------------------------------------------------
 241  * PISCR - Periodic Interrupt Status and Control                11-31
 242  *-----------------------------------------------------------------------
 243  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 244  */
 245 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 246
 247 /*-----------------------------------------------------------------------
 248  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 249  *-----------------------------------------------------------------------
 250  * Reset PLL lock status sticky bit, timer expired status bit and timer
 251  * interrupt status bit
 252  *
 253  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 254  */
 255                         /* up to 50 MHz we use a 1:1 clock */
 256 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 257
 258 /*-----------------------------------------------------------------------
 259  * SCCR - System Clock and reset Control Register               15-27
 260  *-----------------------------------------------------------------------
 261  * Set clock output, timebase and RTC source and divider,
 262  * power management and some other internal clocks
 263  */
 264 #define SCCR_MASK       SCCR_EBDF11
 265                         /* up to 50 MHz we use a 1:1 clock */
 266 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 267                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 268                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 269                          SCCR_DFALCD00)
 270
 271 /*-----------------------------------------------------------------------
 272  *
 273  *-----------------------------------------------------------------------
 274  *
 275  */
 276 #define CONFIG_SYS_DER  0
 277
 278 /*
 279  * Init Memory Controller:
 280  *
 281  * BR0/5 and OR0/5 (FLASH)
 282  */
 283
 284 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 285 #define FLASH_BASE5_PRELIM      0x60000000      /* FLASH bank #1        */
 286
 287 /* used to re-map FLASH both when starting from SRAM or FLASH:
 288  * restrict access enough to keep SRAM working (if any)
 289  * but not too much to meddle with FLASH accesses
 290  */
 291 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 292 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 293
 294 /* FLASH timing */
 295 #define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | \
 296                                  OR_SCY_5_CLK | OR_TRLX)
 297
 298 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 299 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 300 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 301
 302 #define CONFIG_SYS_OR5_REMAP   CONFIG_SYS_OR0_REMAP
 303 #define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_OR0_PRELIM
 304 #define CONFIG_SYS_BR5_PRELIM  ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V )
 305
 306 /*
 307  * BR2/3 and OR2/3 (SDRAM)
 308  *
 309  */
 310 #define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank #0        */
 311 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 312
 313 /* SDRAM timing: Multiplexed addresses                                  */
 314 #define CONFIG_SYS_OR_TIMING_SDRAM     (OR_CSNT_SAM)
 315
 316 #define CONFIG_SYS_OR3_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 317 #define CONFIG_SYS_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 318
 319 /*
 320  * Memory Periodic Timer Prescaler
 321  */
 322
 323 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 324 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 325 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 326
 327 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 328 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 329 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 330
 331 /*
 332  * MAMR settings for SDRAM
 333  */
 334 /* periodic timer for refresh */
 335 #define CONFIG_SYS_MAMR_PTA     97              /* start with divider for 100 MHz       */
 336
 337 /* 8 column SDRAM */
 338 #define CONFIG_SYS_MAMR_8COL \
 339                         ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |    \
 340                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 341                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 342
 343 /*
 344  * JFFS2 partitions
 345  *
 346  */
 347 /* No command line, one static partition, whole device */
 348 #undef CONFIG_CMD_MTDPARTS
 349 #define CONFIG_JFFS2_DEV                "nor0"
 350 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 351 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 352
 353 /* mtdparts command line support */
 354 /*
 355 #define CONFIG_CMD_MTDPARTS
 356 #define MTDIDS_DEFAULT          ""
 357 #define MTDPARTS_DEFAULT        ""
 358 */
 359
 360 #endif  /* __CONFIG_H */