include/configs/M5208EVBE.h

   1 /*
   2  * Configuation settings for the Freescale MCF5208EVBe.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _M5208EVBE_H
  11 #define _M5208EVBE_H
  12
  13 /*
  14  * High Level Configuration Options
  15  * (easy to change)
  16  */
  17 #define CONFIG_MCF520x          /* define processor family */
  18 #define CONFIG_M5208            /* define processor type */
  19
  20 #define CONFIG_MCFUART
  21 #define CONFIG_SYS_UART_PORT            (0)
  22 #define CONFIG_BAUDRATE                 115200
  23
  24 #undef CONFIG_WATCHDOG
  25 #define CONFIG_WATCHDOG_TIMEOUT         5000
  26
  27 /* Command line configuration */
  28 #include <config_cmd_default.h>
  29
  30 #define CONFIG_CMD_CACHE
  31 #define CONFIG_CMD_ELF
  32 #define CONFIG_CMD_FLASH
  33 #undef CONFIG_CMD_I2C
  34 #define CONFIG_CMD_MEMORY
  35 #define CONFIG_CMD_MISC
  36 #define CONFIG_CMD_MII
  37 #define CONFIG_CMD_NET
  38 #define CONFIG_CMD_PING
  39 #define CONFIG_CMD_REGINFO
  40
  41 #define CONFIG_MCFFEC
  42 #ifdef CONFIG_MCFFEC
  43 #       define CONFIG_MII               1
  44 #       define CONFIG_MII_INIT          1
  45 #       define CONFIG_SYS_DISCOVER_PHY
  46 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  47 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  48 #       define CONFIG_HAS_ETH1
  49
  50 #       define CONFIG_SYS_FEC0_PINMUX   0
  51 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  52 #       define MCFFEC_TOUT_LOOP         50000
  53 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  54 #       ifndef CONFIG_SYS_DISCOVER_PHY
  55 #               define FECDUPLEX        FULL
  56 #               define FECSPEED         _100BASET
  57 #       else
  58 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  60 #               endif
  61 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  62 #endif
  63
  64 /* Timer */
  65 #define CONFIG_MCFTMR
  66 #undef CONFIG_MCFPIT
  67
  68 /* I2C */
  69 #define CONFIG_SYS_I2C
  70 #define CONFIG_SYS_I2C_FSL
  71 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  72 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  73 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  74 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  75
  76 #define CONFIG_BOOTDELAY                1       /* autoboot after 5 seconds */
  77 #define CONFIG_UDP_CHECKSUM
  78
  79 #ifdef CONFIG_MCFFEC
  80 #       define CONFIG_ETHADDR   00:e0:0c:bc:e5:60
  81 #       define CONFIG_IPADDR    192.162.1.2
  82 #       define CONFIG_NETMASK   255.255.255.0
  83 #       define CONFIG_SERVERIP  192.162.1.1
  84 #       define CONFIG_GATEWAYIP 192.162.1.1
  85 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  86 #endif                          /* CONFIG_MCFFEC */
  87
  88 #define CONFIG_HOSTNAME         M5208EVBe
  89 #define CONFIG_EXTRA_ENV_SETTINGS               \
  90         "netdev=eth0\0"                         \
  91         "loadaddr=40010000\0"                   \
  92         "u-boot=u-boot.bin\0"                   \
  93         "load=tftp ${loadaddr) ${u-boot}\0"     \
  94         "upd=run load; run prog\0"              \
  95         "prog=prot off 0 3ffff;"                \
  96         "era 0 3ffff;"                          \
  97         "cp.b ${loadaddr} 0 ${filesize};"       \
  98         "save\0"                                \
  99         ""
 100
 101 #define CONFIG_PRAM             512     /* 512 KB */
 102 #define CONFIG_SYS_PROMPT       "-> "
 103 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 104
 105 #ifdef CONFIG_CMD_KGDB
 106 #       define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size */
 107 #else
 108 #       define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size */
 109 #endif
 110
 111 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 112 #define CONFIG_SYS_MAXARGS      16              /* max number of cmd args */
 113 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Arg Buf Sz */
 114 #define CONFIG_SYS_LOAD_ADDR    0x40010000
 115
 116 #define CONFIG_SYS_CLK          166666666       /* CPU Core Clock */
 117 #define CONFIG_SYS_PLL_ODR      0x36
 118 #define CONFIG_SYS_PLL_FDR      0x7D
 119
 120 #define CONFIG_SYS_MBAR         0xFC000000
 121
 122 /*
 123  * Low Level Configuration Settings
 124  * (address mappings, register initial values, etc.)
 125  * You should know what you are doing if you make changes here.
 126  */
 127 /* Definitions for initial stack pointer and data area (in DPRAM) */
 128 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 129 #define CONFIG_SYS_INIT_RAM_SIZE                0x4000  /* Size of used area in internal SRAM */
 130 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 131 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 132 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 133
 134 /*
 135  * Start addresses for the final memory configuration
 136  * (Set up by the startup code)
 137  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 138  */
 139 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 140 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
 141 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 142 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 143 #define CONFIG_SYS_SDRAM_CTRL           0xE1002000
 144 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 145 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 146
 147 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 148 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 149
 150 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 151 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 152
 153 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 154 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 155
 156 /*
 157  * For booting Linux, the board info and command line data
 158  * have to be in the first 8 MB of memory, since this is
 159  * the maximum mapped by the Linux kernel during initialization ??
 160  */
 161 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 162 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 163
 164 /* FLASH organization */
 165 #define CONFIG_SYS_FLASH_CFI
 166 #ifdef CONFIG_SYS_FLASH_CFI
 167 #       define CONFIG_FLASH_CFI_DRIVER          1
 168 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 169 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 170 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 171 #       define CONFIG_SYS_MAX_FLASH_SECT        254     /* max number of sectors on one chip */
 172 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 173 #endif
 174
 175 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 176
 177 /*
 178  * Configuration for environment
 179  * Environment is embedded in u-boot in the second sector of the flash
 180  */
 181 #define CONFIG_ENV_OFFSET               0x2000
 182 #define CONFIG_ENV_SIZE                 0x1000
 183 #define CONFIG_ENV_SECT_SIZE            0x2000
 184 #define CONFIG_ENV_IS_IN_FLASH          1
 185
 186 /* Cache Configuration */
 187 #define CONFIG_SYS_CACHELINE_SIZE       16
 188
 189 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 190                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 191 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 192                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 193 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 194 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 195                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 196                                          CF_ACR_EN | CF_ACR_SM_ALL)
 197 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 198                                          CF_CACR_DISD | CF_CACR_INVI | \
 199                                          CF_CACR_CEIB | CF_CACR_DCM | \
 200                                          CF_CACR_EUSP)
 201
 202 /* Chipselect bank definitions */
 203 /*
 204  * CS0 - NOR Flash
 205  * CS1 - Available
 206  * CS2 - Available
 207  * CS3 - Available
 208  * CS4 - Available
 209  * CS5 - Available
 210  */
 211 #define CONFIG_SYS_CS0_BASE             0
 212 #define CONFIG_SYS_CS0_MASK             0x007F0001
 213 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 214
 215 #endif                          /* _M5208EVBE_H */