include/configs/M5235EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5329 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5235EVB_H
  15 #define _M5235EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24 #define CONFIG_BAUDRATE         115200
  25
  26 #undef CONFIG_WATCHDOG
  27 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  28
  29 /*
  30  * BOOTP options
  31  */
  32 #define CONFIG_BOOTP_BOOTFILESIZE
  33 #define CONFIG_BOOTP_BOOTPATH
  34 #define CONFIG_BOOTP_GATEWAY
  35 #define CONFIG_BOOTP_HOSTNAME
  36
  37 /* Command line configuration */
  38 #define CONFIG_CMD_PCI
  39 #define CONFIG_CMD_REGINFO
  40
  41 #define CONFIG_MCFFEC
  42 #ifdef CONFIG_MCFFEC
  43 #       define CONFIG_MII               1
  44 #       define CONFIG_MII_INIT          1
  45 #       define CONFIG_SYS_DISCOVER_PHY
  46 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  47 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  48
  49 #       define CONFIG_SYS_FEC0_PINMUX           0
  50 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  51 #       define MCFFEC_TOUT_LOOP         50000
  52 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  53 #       ifndef CONFIG_SYS_DISCOVER_PHY
  54 #               define FECDUPLEX        FULL
  55 #               define FECSPEED         _100BASET
  56 #       else
  57 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  58 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  59 #               endif
  60 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  61 #endif
  62
  63 /* Timer */
  64 #define CONFIG_MCFTMR
  65 #undef CONFIG_MCFPIT
  66
  67 /* I2C */
  68 #define CONFIG_SYS_I2C
  69 #define CONFIG_SYS_i2C_FSL
  70 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  71 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  72 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
  73 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  74 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio->par_qspi)
  75 #define CONFIG_SYS_I2C_PINMUX_CLR       ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
  76 #define CONFIG_SYS_I2C_PINMUX_SET       (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
  77
  78 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  79 #define CONFIG_BOOTFILE         "u-boot.bin"
  80 #ifdef CONFIG_MCFFEC
  81 #       define CONFIG_IPADDR    192.162.1.2
  82 #       define CONFIG_NETMASK   255.255.255.0
  83 #       define CONFIG_SERVERIP  192.162.1.1
  84 #       define CONFIG_GATEWAYIP 192.162.1.1
  85 #endif                          /* FEC_ENET */
  86
  87 #define CONFIG_HOSTNAME         M5235EVB
  88 #define CONFIG_EXTRA_ENV_SETTINGS               \
  89         "netdev=eth0\0"                         \
  90         "loadaddr=10000\0"                      \
  91         "u-boot=u-boot.bin\0"                   \
  92         "load=tftp ${loadaddr) ${u-boot}\0"     \
  93         "upd=run load; run prog\0"              \
  94         "prog=prot off ffe00000 ffe3ffff;"      \
  95         "era ffe00000 ffe3ffff;"                \
  96         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  97         "save\0"                                \
  98         ""
  99
 100 #define CONFIG_PRAM             512     /* 512 KB */
 101 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 102
 103 #if defined(CONFIG_KGDB)
 104 #       define CONFIG_SYS_CBSIZE                1024    /* Console I/O Buffer Size */
 105 #else
 106 #       define CONFIG_SYS_CBSIZE                256     /* Console I/O Buffer Size */
 107 #endif
 108
 109 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 110 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 111 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 112 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE+0x20000)
 113
 114 #define CONFIG_SYS_CLK                  75000000
 115 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 116
 117 #define CONFIG_SYS_MBAR         0x40000000
 118
 119 /*
 120  * Low Level Configuration Settings
 121  * (address mappings, register initial values, etc.)
 122  * You should know what you are doing if you make changes here.
 123  */
 124 /*-----------------------------------------------------------------------
 125  * Definitions for initial stack pointer and data area (in DPRAM)
 126  */
 127 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 128 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 129 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 130 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
 131 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 132
 133 /*-----------------------------------------------------------------------
 134  * Start addresses for the final memory configuration
 135  * (Set up by the startup code)
 136  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 137  */
 138 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 139 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 140
 141 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 142 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 143
 144 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 145 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 146
 147 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 148 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 149
 150 /*
 151  * For booting Linux, the board info and command line data
 152  * have to be in the first 8 MB of memory, since this is
 153  * the maximum mapped by the Linux kernel during initialization ??
 154  */
 155 /* Initial Memory map for Linux */
 156 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 157 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 158
 159 /*-----------------------------------------------------------------------
 160  * FLASH organization
 161  */
 162 #define CONFIG_SYS_FLASH_CFI
 163 #ifdef CONFIG_SYS_FLASH_CFI
 164 #       define CONFIG_FLASH_CFI_DRIVER  1
 165 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 166 #ifdef NORFLASH_PS32BIT
 167 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_32BIT
 168 #else
 169 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 170 #endif
 171 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 172 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 173 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 174 #endif
 175
 176 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 177
 178 /* Configuration for environment
 179  * Environment is embedded in u-boot in the second sector of the flash
 180  */
 181 #define CONFIG_ENV_IS_IN_FLASH  1
 182
 183 #define LDS_BOARD_TEXT \
 184         . = DEFINED(env_offset) ? env_offset : .; \
 185         common/env_embedded.o (.text);
 186
 187 #ifdef NORFLASH_PS32BIT
 188 #       define CONFIG_ENV_OFFSET                (0x8000)
 189 #       define CONFIG_ENV_SIZE          0x4000
 190 #       define CONFIG_ENV_SECT_SIZE     0x4000
 191 #else
 192 #       define CONFIG_ENV_OFFSET                (0x4000)
 193 #       define CONFIG_ENV_SIZE          0x2000
 194 #       define CONFIG_ENV_SECT_SIZE     0x2000
 195 #endif
 196
 197 /*-----------------------------------------------------------------------
 198  * Cache Configuration
 199  */
 200 #define CONFIG_SYS_CACHELINE_SIZE       16
 201
 202 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 203                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 204 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 205                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 206 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV)
 207 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 208                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 209                                          CF_ACR_EN | CF_ACR_SM_ALL)
 210 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 211                                          CF_CACR_CEIB | CF_CACR_DCM | \
 212                                          CF_CACR_EUSP)
 213
 214 /*-----------------------------------------------------------------------
 215  * Chipselect bank definitions
 216  */
 217 /*
 218  * CS0 - NOR Flash 1, 2, 4, or 8MB
 219  * CS1 - Available
 220  * CS2 - Available
 221  * CS3 - Available
 222  * CS4 - Available
 223  * CS5 - Available
 224  * CS6 - Available
 225  * CS7 - Available
 226  */
 227 #ifdef NORFLASH_PS32BIT
 228 #       define CONFIG_SYS_CS0_BASE      0xFFC00000
 229 #       define CONFIG_SYS_CS0_MASK      0x003f0001
 230 #       define CONFIG_SYS_CS0_CTRL      0x00001D00
 231 #else
 232 #       define CONFIG_SYS_CS0_BASE      0xFFE00000
 233 #       define CONFIG_SYS_CS0_MASK      0x001f0001
 234 #       define CONFIG_SYS_CS0_CTRL      0x00001D80
 235 #endif
 236
 237 #endif                          /* _M5329EVB_H */