include/configs/M5235EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5329 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5235EVB_H
  15 #define _M5235EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24
  25 #undef CONFIG_WATCHDOG
  26 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  27
  28 /*
  29  * BOOTP options
  30  */
  31 #define CONFIG_BOOTP_BOOTFILESIZE
  32 #define CONFIG_BOOTP_BOOTPATH
  33 #define CONFIG_BOOTP_GATEWAY
  34 #define CONFIG_BOOTP_HOSTNAME
  35
  36 #define CONFIG_MCFFEC
  37 #ifdef CONFIG_MCFFEC
  38 #       define CONFIG_MII               1
  39 #       define CONFIG_MII_INIT          1
  40 #       define CONFIG_SYS_DISCOVER_PHY
  41 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  42 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  43
  44 #       define CONFIG_SYS_FEC0_PINMUX           0
  45 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  46 #       define MCFFEC_TOUT_LOOP         50000
  47 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  48 #       ifndef CONFIG_SYS_DISCOVER_PHY
  49 #               define FECDUPLEX        FULL
  50 #               define FECSPEED         _100BASET
  51 #       else
  52 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  53 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  54 #               endif
  55 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  56 #endif
  57
  58 /* Timer */
  59 #define CONFIG_MCFTMR
  60 #undef CONFIG_MCFPIT
  61
  62 /* I2C */
  63 #define CONFIG_SYS_I2C
  64 #define CONFIG_SYS_i2C_FSL
  65 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  66 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  67 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
  68 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  69 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio->par_qspi)
  70 #define CONFIG_SYS_I2C_PINMUX_CLR       ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
  71 #define CONFIG_SYS_I2C_PINMUX_SET       (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
  72
  73 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  74 #define CONFIG_BOOTFILE         "u-boot.bin"
  75 #ifdef CONFIG_MCFFEC
  76 #       define CONFIG_IPADDR    192.162.1.2
  77 #       define CONFIG_NETMASK   255.255.255.0
  78 #       define CONFIG_SERVERIP  192.162.1.1
  79 #       define CONFIG_GATEWAYIP 192.162.1.1
  80 #endif                          /* FEC_ENET */
  81
  82 #define CONFIG_HOSTNAME         M5235EVB
  83 #define CONFIG_EXTRA_ENV_SETTINGS               \
  84         "netdev=eth0\0"                         \
  85         "loadaddr=10000\0"                      \
  86         "u-boot=u-boot.bin\0"                   \
  87         "load=tftp ${loadaddr) ${u-boot}\0"     \
  88         "upd=run load; run prog\0"              \
  89         "prog=prot off ffe00000 ffe3ffff;"      \
  90         "era ffe00000 ffe3ffff;"                \
  91         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  92         "save\0"                                \
  93         ""
  94
  95 #define CONFIG_PRAM             512     /* 512 KB */
  96 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  97
  98 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
  99 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 100 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE+0x20000)
 101
 102 #define CONFIG_SYS_CLK                  75000000
 103 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 104
 105 #define CONFIG_SYS_MBAR         0x40000000
 106
 107 /*
 108  * Low Level Configuration Settings
 109  * (address mappings, register initial values, etc.)
 110  * You should know what you are doing if you make changes here.
 111  */
 112 /*-----------------------------------------------------------------------
 113  * Definitions for initial stack pointer and data area (in DPRAM)
 114  */
 115 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 116 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 117 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 118 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
 119 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 120
 121 /*-----------------------------------------------------------------------
 122  * Start addresses for the final memory configuration
 123  * (Set up by the startup code)
 124  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 125  */
 126 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 127 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 128
 129 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 130 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 131
 132 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 133 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 134
 135 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 136 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 137
 138 /*
 139  * For booting Linux, the board info and command line data
 140  * have to be in the first 8 MB of memory, since this is
 141  * the maximum mapped by the Linux kernel during initialization ??
 142  */
 143 /* Initial Memory map for Linux */
 144 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 145 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 146
 147 /*-----------------------------------------------------------------------
 148  * FLASH organization
 149  */
 150 #define CONFIG_SYS_FLASH_CFI
 151 #ifdef CONFIG_SYS_FLASH_CFI
 152 #       define CONFIG_FLASH_CFI_DRIVER  1
 153 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 154 #ifdef NORFLASH_PS32BIT
 155 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_32BIT
 156 #else
 157 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 158 #endif
 159 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 160 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 161 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 162 #endif
 163
 164 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 165
 166 /* Configuration for environment
 167  * Environment is embedded in u-boot in the second sector of the flash
 168  */
 169
 170 #define LDS_BOARD_TEXT \
 171         . = DEFINED(env_offset) ? env_offset : .; \
 172         env/embedded.o(.text);
 173
 174 #ifdef NORFLASH_PS32BIT
 175 #       define CONFIG_ENV_OFFSET                (0x8000)
 176 #       define CONFIG_ENV_SIZE          0x4000
 177 #       define CONFIG_ENV_SECT_SIZE     0x4000
 178 #else
 179 #       define CONFIG_ENV_OFFSET                (0x4000)
 180 #       define CONFIG_ENV_SIZE          0x2000
 181 #       define CONFIG_ENV_SECT_SIZE     0x2000
 182 #endif
 183
 184 /*-----------------------------------------------------------------------
 185  * Cache Configuration
 186  */
 187 #define CONFIG_SYS_CACHELINE_SIZE       16
 188
 189 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 190                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 191 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 192                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 193 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV)
 194 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 195                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 196                                          CF_ACR_EN | CF_ACR_SM_ALL)
 197 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 198                                          CF_CACR_CEIB | CF_CACR_DCM | \
 199                                          CF_CACR_EUSP)
 200
 201 /*-----------------------------------------------------------------------
 202  * Chipselect bank definitions
 203  */
 204 /*
 205  * CS0 - NOR Flash 1, 2, 4, or 8MB
 206  * CS1 - Available
 207  * CS2 - Available
 208  * CS3 - Available
 209  * CS4 - Available
 210  * CS5 - Available
 211  * CS6 - Available
 212  * CS7 - Available
 213  */
 214 #ifdef NORFLASH_PS32BIT
 215 #       define CONFIG_SYS_CS0_BASE      0xFFC00000
 216 #       define CONFIG_SYS_CS0_MASK      0x003f0001
 217 #       define CONFIG_SYS_CS0_CTRL      0x00001D00
 218 #else
 219 #       define CONFIG_SYS_CS0_BASE      0xFFE00000
 220 #       define CONFIG_SYS_CS0_MASK      0x001f0001
 221 #       define CONFIG_SYS_CS0_CTRL      0x00001D80
 222 #endif
 223
 224 #endif                          /* _M5329EVB_H */