include/configs/M5253DEMO.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  */
   5
   6 #ifndef _M5253DEMO_H
   7 #define _M5253DEMO_H
   8
   9 #define CONFIG_MCFTMR
  10
  11 #define CONFIG_MCFUART
  12 #define CONFIG_SYS_UART_PORT            (0)
  13
  14 #undef CONFIG_WATCHDOG          /* disable watchdog */
  15
  16
  17 /* Configuration for environment
  18  * Environment is embedded in u-boot in the second sector of the flash
  19  */
  20
  21 #define LDS_BOARD_TEXT \
  22         . = DEFINED(env_offset) ? env_offset : .; \
  23         env/embedded.o(.text*);
  24
  25 /*
  26  * Command line configuration.
  27  */
  28
  29 #ifdef CONFIG_IDE
  30 /* ATA */
  31 #       define CONFIG_IDE_RESET         1
  32 #       define CONFIG_IDE_PREINIT       1
  33 #       define CONFIG_ATAPI
  34 #       undef CONFIG_LBA48
  35
  36 #       define CONFIG_SYS_IDE_MAXBUS            1
  37 #       define CONFIG_SYS_IDE_MAXDEVICE 2
  38
  39 #       define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  40 #       define CONFIG_SYS_ATA_IDE0_OFFSET       0
  41
  42 #       define CONFIG_SYS_ATA_DATA_OFFSET       0xA0    /* Offset for data I/O */
  43 #       define CONFIG_SYS_ATA_REG_OFFSET        0xA0    /* Offset for normal register accesses */
  44 #       define CONFIG_SYS_ATA_ALT_OFFSET        0xC0    /* Offset for alternate registers */
  45 #       define CONFIG_SYS_ATA_STRIDE            4       /* Interval between registers */
  46 #endif
  47
  48 #define CONFIG_DRIVER_DM9000
  49 #ifdef CONFIG_DRIVER_DM9000
  50 #       define CONFIG_DM9000_BASE       (CONFIG_SYS_CS1_BASE | 0x300)
  51 #       define DM9000_IO                CONFIG_DM9000_BASE
  52 #       define DM9000_DATA              (CONFIG_DM9000_BASE + 4)
  53 #       undef CONFIG_DM9000_DEBUG
  54 #       define CONFIG_DM9000_BYTE_SWAPPED
  55
  56 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
  57
  58 #       define CONFIG_EXTRA_ENV_SETTINGS                \
  59                 "netdev=eth0\0"                         \
  60                 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
  61                 "loadaddr=10000\0"                      \
  62                 "u-boot=u-boot.bin\0"                   \
  63                 "load=tftp ${loadaddr) ${u-boot}\0"     \
  64                 "upd=run load; run prog\0"              \
  65                 "prog=prot off 0xff800000 0xff82ffff;"  \
  66                 "era 0xff800000 0xff82ffff;"            \
  67                 "cp.b ${loadaddr} 0xff800000 ${filesize};"      \
  68                 "save\0"                                \
  69                 ""
  70 #endif
  71
  72 #define CONFIG_HOSTNAME         "M5253DEMO"
  73
  74 /* I2C */
  75 #define CONFIG_SYS_I2C
  76 #define CONFIG_SYS_I2C_FSL
  77 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  78 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  79 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000280
  80 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  81 #define CONFIG_SYS_I2C_PINMUX_REG       (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
  82 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFFFE7FF)
  83 #define CONFIG_SYS_I2C_PINMUX_SET       (0)
  84
  85 #define CONFIG_SYS_LOAD_ADDR            0x00100000
  86
  87 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
  88 #define CONFIG_SYS_FAST_CLK
  89 #ifdef CONFIG_SYS_FAST_CLK
  90 #       define CONFIG_SYS_PLLCR 0x1243E054
  91 #       define CONFIG_SYS_CLK           140000000
  92 #else
  93 #       define CONFIG_SYS_PLLCR 0x135a4140
  94 #       define CONFIG_SYS_CLK           70000000
  95 #endif
  96
  97 /*
  98  * Low Level Configuration Settings
  99  * (address mappings, register initial values, etc.)
 100  * You should know what you are doing if you make changes here.
 101  */
 102
 103 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 104 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
 105
 106 /*
 107  * Definitions for initial stack pointer and data area (in DPRAM)
 108  */
 109 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 110 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 111 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 112 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 113
 114 /*
 115  * Start addresses for the final memory configuration
 116  * (Set up by the startup code)
 117  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 118  */
 119 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 120 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 121
 122 #ifdef CONFIG_MONITOR_IS_IN_RAM
 123 #       define CONFIG_SYS_MONITOR_BASE  0x20000
 124 #else
 125 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 126 #endif
 127
 128 #define CONFIG_SYS_MONITOR_LEN          0x40000
 129 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 130 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 131
 132 /*
 133  * For booting Linux, the board info and command line data
 134  * have to be in the first 8 MB of memory, since this is
 135  * the maximum mapped by the Linux kernel during initialization ??
 136  */
 137 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 138 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 139
 140 /* FLASH organization */
 141 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 142 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 143 #define CONFIG_SYS_MAX_FLASH_SECT       2048    /* max number of sectors on one chip */
 144 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 145
 146 #define FLASH_SST6401B          0x200
 147 #define SST_ID_xF6401B          0x236D236D
 148
 149 #ifdef CONFIG_SYS_FLASH_CFI
 150 /*
 151  * Unable to use CFI driver, due to incompatible sector erase command by SST.
 152  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 153  * 0x30 is block erase in SST
 154  */
 155 #       define CONFIG_SYS_FLASH_SIZE            0x800000
 156 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 157 #       define CONFIG_FLASH_CFI_LEGACY
 158 #else
 159 #       define CONFIG_SYS_SST_SECT              2048
 160 #       define CONFIG_SYS_SST_SECTSZ            0x1000
 161 #       define CONFIG_SYS_FLASH_WRITE_TOUT      500
 162 #endif
 163
 164 /* Cache Configuration */
 165 #define CONFIG_SYS_CACHELINE_SIZE       16
 166
 167 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 168                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 169 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 170                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 171 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 172 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 173                                          CF_ADDRMASK(8) | \
 174                                          CF_ACR_EN | CF_ACR_SM_ALL)
 175 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 176                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 177                                          CF_ACR_EN | CF_ACR_SM_ALL)
 178 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 179                                          CF_CACR_DBWE)
 180
 181 /* Port configuration */
 182 #define CONFIG_SYS_FECI2C               0xF0
 183
 184 #define CONFIG_SYS_CS0_BASE             0xFF800000
 185 #define CONFIG_SYS_CS0_MASK             0x007F0021
 186 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 187
 188 #define CONFIG_SYS_CS1_BASE             0xE0000000
 189 #define CONFIG_SYS_CS1_MASK             0x00000001
 190 #define CONFIG_SYS_CS1_CTRL             0x00003DD8
 191
 192 /*-----------------------------------------------------------------------
 193  * Port configuration
 194  */
 195 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 196 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 197 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 198 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 199 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 200 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 201 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 202
 203 #endif                          /* _M5253DEMO_H */