include/configs/M5253DEMO.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _M5253DEMO_H
  25 #define _M5253DEMO_H
  26
  27 #define CONFIG_MCF52x2          /* define processor family */
  28 #define CONFIG_M5253            /* define processor type */
  29 #define CONFIG_M5253DEMO        /* define board type */
  30
  31 #define CONFIG_MCFTMR
  32
  33 #define CONFIG_MCFUART
  34 #define CONFIG_SYS_UART_PORT            (0)
  35 #define CONFIG_BAUDRATE         115200
  36 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600 , 19200 , 38400 , 57600, 115200 }
  37
  38 #undef CONFIG_WATCHDOG          /* disable watchdog */
  39
  40 #define CONFIG_BOOTDELAY        5
  41
  42 /* Configuration for environment
  43  * Environment is embedded in u-boot in the second sector of the flash
  44  */
  45 #ifdef CONFIG_MONITOR_IS_IN_RAM
  46 #       define CONFIG_ENV_OFFSET                0x4000
  47 #       define CONFIG_ENV_SECT_SIZE     0x1000
  48 #       define CONFIG_ENV_IS_IN_FLASH   1
  49 #else
  50 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x4000)
  51 #       define CONFIG_ENV_SECT_SIZE     0x1000
  52 #       define CONFIG_ENV_IS_IN_FLASH   1
  53 #endif
  54
  55 /*
  56  * Command line configuration.
  57  */
  58 #include <config_cmd_default.h>
  59
  60 #define CONFIG_CMD_CACHE
  61 #define CONFIG_CMD_LOADB
  62 #define CONFIG_CMD_LOADS
  63 #define CONFIG_CMD_EXT2
  64 #define CONFIG_CMD_FAT
  65 #define CONFIG_CMD_IDE
  66 #define CONFIG_CMD_MEMORY
  67 #define CONFIG_CMD_MISC
  68 #define CONFIG_CMD_PING
  69
  70 #ifdef CONFIG_CMD_IDE
  71 /* ATA */
  72 #       define CONFIG_DOS_PARTITION
  73 #       define CONFIG_MAC_PARTITION
  74 #       define CONFIG_IDE_RESET         1
  75 #       define CONFIG_IDE_PREINIT       1
  76 #       define CONFIG_ATAPI
  77 #       undef CONFIG_LBA48
  78
  79 #       define CONFIG_SYS_IDE_MAXBUS            1
  80 #       define CONFIG_SYS_IDE_MAXDEVICE 2
  81
  82 #       define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  83 #       define CONFIG_SYS_ATA_IDE0_OFFSET       0
  84
  85 #       define CONFIG_SYS_ATA_DATA_OFFSET       0xA0    /* Offset for data I/O */
  86 #       define CONFIG_SYS_ATA_REG_OFFSET        0xA0    /* Offset for normal register accesses */
  87 #       define CONFIG_SYS_ATA_ALT_OFFSET        0xC0    /* Offset for alternate registers */
  88 #       define CONFIG_SYS_ATA_STRIDE            4       /* Interval between registers */
  89 #endif
  90
  91 #define CONFIG_NET_MULTI                1
  92 #define CONFIG_DRIVER_DM9000
  93 #ifdef CONFIG_DRIVER_DM9000
  94 #       define CONFIG_DM9000_BASE       (CONFIG_SYS_CS1_BASE | 0x300)
  95 #       define DM9000_IO                CONFIG_DM9000_BASE
  96 #       define DM9000_DATA              (CONFIG_DM9000_BASE + 4)
  97 #       undef CONFIG_DM9000_DEBUG
  98
  99 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 100
 101 #       define CONFIG_EXTRA_ENV_SETTINGS                \
 102                 "netdev=eth0\0"                         \
 103                 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"  \
 104                 "loadaddr=10000\0"                      \
 105                 "u-boot=u-boot.bin\0"                   \
 106                 "load=tftp ${loadaddr) ${u-boot}\0"     \
 107                 "upd=run load; run prog\0"              \
 108                 "prog=prot off 0xff800000 0xff82ffff;"  \
 109                 "era 0xff800000 0xff82ffff;"            \
 110                 "cp.b ${loadaddr} 0xff800000 ${filesize};"      \
 111                 "save\0"                                \
 112                 ""
 113 #endif
 114
 115 #define CONFIG_HOSTNAME         M5253DEMO
 116
 117 /* I2C */
 118 #define CONFIG_FSL_I2C
 119 #define CONFIG_HARD_I2C         /* I2C with hw support */
 120 #define CONFIG_SYS_I2C_SPEED            80000
 121 #define CONFIG_SYS_I2C_SLAVE            0x7F
 122 #define CONFIG_SYS_I2C_OFFSET           0x00000280
 123 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 124 #define CONFIG_SYS_I2C_PINMUX_REG       (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
 125 #define CONFIG_SYS_I2C_PINMUX_CLR       (0xFFFFE7FF)
 126 #define CONFIG_SYS_I2C_PINMUX_SET       (0)
 127
 128 #define CONFIG_SYS_PROMPT               "=> "
 129 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 130
 131 #if defined(CONFIG_CMD_KGDB)
 132 #       define CONFIG_SYS_CBSIZE                1024    /* Console I/O Buffer Size */
 133 #else
 134 #       define CONFIG_SYS_CBSIZE                256     /* Console I/O Buffer Size */
 135 #endif
 136 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 137 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 138 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 139
 140 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 141
 142 #define CONFIG_SYS_MEMTEST_START        0x400
 143 #define CONFIG_SYS_MEMTEST_END          0x380000
 144
 145 #define CONFIG_SYS_HZ                   1000
 146
 147 #undef CONFIG_SYS_PLL_BYPASS            /* bypass PLL for test purpose */
 148 #define CONFIG_SYS_FAST_CLK
 149 #ifdef CONFIG_SYS_FAST_CLK
 150 #       define CONFIG_SYS_PLLCR 0x1243E054
 151 #       define CONFIG_SYS_CLK           140000000
 152 #else
 153 #       define CONFIG_SYS_PLLCR 0x135a4140
 154 #       define CONFIG_SYS_CLK           70000000
 155 #endif
 156
 157 /*
 158  * Low Level Configuration Settings
 159  * (address mappings, register initial values, etc.)
 160  * You should know what you are doing if you make changes here.
 161  */
 162
 163 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 164 #define CONFIG_SYS_MBAR2                0x80000000      /* Module Base Addrs 2 */
 165
 166 /*
 167  * Definitions for initial stack pointer and data area (in DPRAM)
 168  */
 169 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 170 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 171 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 172 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 173
 174 /*
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 180 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 181
 182 #ifdef CONFIG_MONITOR_IS_IN_RAM
 183 #       define CONFIG_SYS_MONITOR_BASE  0x20000
 184 #else
 185 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 186 #endif
 187
 188 #define CONFIG_SYS_MONITOR_LEN          0x40000
 189 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 190 #define CONFIG_SYS_BOOTPARAMS_LEN       (64*1024)
 191
 192 /*
 193  * For booting Linux, the board info and command line data
 194  * have to be in the first 8 MB of memory, since this is
 195  * the maximum mapped by the Linux kernel during initialization ??
 196  */
 197 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 198 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 199
 200 /* FLASH organization */
 201 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 202 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 203 #define CONFIG_SYS_MAX_FLASH_SECT       2048    /* max number of sectors on one chip */
 204 #define CONFIG_SYS_FLASH_ERASE_TOUT     1000
 205
 206 #define FLASH_SST6401B          0x200
 207 #define SST_ID_xF6401B          0x236D236D
 208
 209 #undef CONFIG_SYS_FLASH_CFI
 210 #ifdef CONFIG_SYS_FLASH_CFI
 211 /*
 212  * Unable to use CFI driver, due to incompatible sector erase command by SST.
 213  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 214  * 0x30 is block erase in SST
 215  */
 216 #       define CONFIG_FLASH_CFI_DRIVER  1
 217 #       define CONFIG_SYS_FLASH_SIZE            0x800000
 218 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 219 #       define CONFIG_FLASH_CFI_LEGACY
 220 #else
 221 #       define CONFIG_SYS_SST_SECT              2048
 222 #       define CONFIG_SYS_SST_SECTSZ            0x1000
 223 #       define CONFIG_SYS_FLASH_WRITE_TOUT      500
 224 #endif
 225
 226 /* Cache Configuration */
 227 #define CONFIG_SYS_CACHELINE_SIZE       16
 228
 229 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 230                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 231 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 232                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 233 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 234 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_FLASH_BASE | \
 235                                          CF_ADDRMASK(8) | \
 236                                          CF_ACR_EN | CF_ACR_SM_ALL)
 237 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 238                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 239                                          CF_ACR_EN | CF_ACR_SM_ALL)
 240 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 241                                          CF_CACR_DBWE)
 242
 243 /* Port configuration */
 244 #define CONFIG_SYS_FECI2C               0xF0
 245
 246 #define CONFIG_SYS_CS0_BASE             0xFF800000
 247 #define CONFIG_SYS_CS0_MASK             0x007F0021
 248 #define CONFIG_SYS_CS0_CTRL             0x00001D80
 249
 250 #define CONFIG_SYS_CS1_BASE             0xE0000000
 251 #define CONFIG_SYS_CS1_MASK             0x00000001
 252 #define CONFIG_SYS_CS1_CTRL             0x00003DD8
 253
 254 /*-----------------------------------------------------------------------
 255  * Port configuration
 256  */
 257 #define CONFIG_SYS_GPIO_FUNC            0x00000008      /* Set gpio pins: none */
 258 #define CONFIG_SYS_GPIO1_FUNC           0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 259 #define CONFIG_SYS_GPIO_EN              0x00000008      /* Set gpio output enable */
 260 #define CONFIG_SYS_GPIO1_EN             0x00c70000      /* Set gpio output enable */
 261 #define CONFIG_SYS_GPIO_OUT             0x00000008      /* Set outputs to default state */
 262 #define CONFIG_SYS_GPIO1_OUT            0x00c70000      /* Set outputs to default state */
 263 #define CONFIG_SYS_GPIO1_LED            0x00400000      /* user led */
 264
 265 #endif                          /* _M5253DEMO_H */