include/configs/M5253DEMO.h

   1 /*
   2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   3  * Hayden Fraser (Hayden.Fraser@freescale.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _M5253DEMO_H
  25 #define _M5253DEMO_H
  26
  27 #define CONFIG_MCF52x2          /* define processor family */
  28 #define CONFIG_M5253            /* define processor type */
  29 #define CONFIG_M5253DEMO        /* define board type */
  30
  31 #define CONFIG_MCFTMR
  32
  33 #define CONFIG_MCFUART
  34 #define CFG_UART_PORT           (0)
  35 #define CONFIG_BAUDRATE         115200
  36 #define CFG_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
  37
  38 #undef CONFIG_WATCHDOG          /* disable watchdog */
  39
  40 #define CONFIG_BOOTDELAY        5
  41
  42 /* Configuration for environment
  43  * Environment is embedded in u-boot in the second sector of the flash
  44  */
  45 #ifdef CONFIG_MONITOR_IS_IN_RAM
  46 #       define CFG_ENV_OFFSET           0x4000
  47 #       define CFG_ENV_SECT_SIZE        0x1000
  48 #       define CFG_ENV_IS_IN_FLASH      1
  49 #else
  50 #       define CFG_ENV_ADDR             (CFG_FLASH_BASE + 0x4000)
  51 #       define CFG_ENV_SECT_SIZE        0x1000
  52 #       define CFG_ENV_IS_IN_FLASH      1
  53 #endif
  54
  55 /*
  56  * Command line configuration.
  57  */
  58 #include <config_cmd_default.h>
  59
  60 #define CONFIG_CMD_LOADB
  61 #define CONFIG_CMD_LOADS
  62 #define CONFIG_CMD_EXT2
  63 #define CONFIG_CMD_FAT
  64 #define CONFIG_CMD_IDE
  65 #define CONFIG_CMD_MEMORY
  66 #define CONFIG_CMD_MISC
  67 #define CONFIG_CMD_PING
  68
  69 #ifdef CONFIG_CMD_IDE
  70 /* ATA */
  71 #       define CONFIG_DOS_PARTITION
  72 #       define CONFIG_MAC_PARTITION
  73 #       define CONFIG_IDE_RESET         1
  74 #       define CONFIG_IDE_PREINIT       1
  75 #       define CONFIG_ATAPI
  76 #       undef CONFIG_LBA48
  77
  78 #       define CFG_IDE_MAXBUS           1
  79 #       define CFG_IDE_MAXDEVICE        2
  80
  81 #       define CFG_ATA_BASE_ADDR        (CFG_MBAR2 + 0x800)
  82 #       define CFG_ATA_IDE0_OFFSET      0
  83
  84 #       define CFG_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O */
  85 #       define CFG_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
  86 #       define CFG_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers */
  87 #       define CFG_ATA_STRIDE           4       /* Interval between registers */
  88 #       define _IO_BASE                 0
  89 #endif
  90
  91 #define CONFIG_DRIVER_DM9000
  92 #ifdef CONFIG_DRIVER_DM9000
  93 #       define CONFIG_DM9000_BASE       ((CFG_CSAR1 << 16) | 0x300)
  94 #       define DM9000_IO                CONFIG_DM9000_BASE
  95 #       define DM9000_DATA              (CONFIG_DM9000_BASE + 4)
  96 #       undef CONFIG_DM9000_DEBUG
  97
  98 #       define CONFIG_ETHADDR           00:e0:0c:bc:e5:60
  99 #       define CONFIG_IPADDR            10.82.121.249
 100 #       define CONFIG_NETMASK           255.255.252.0
 101 #       define CONFIG_SERVERIP          10.82.120.80
 102 #       define CONFIG_GATEWAYIP         10.82.123.254
 103 #       define CONFIG_OVERWRITE_ETHADDR_ONCE
 104
 105 #       define CONFIG_EXTRA_ENV_SETTINGS                \
 106                 "netdev=eth0\0"                         \
 107                 "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
 108                 "loadaddr=10000\0"                      \
 109                 "u-boot=u-boot.bin\0"                   \
 110                 "load=tftp ${loadaddr) ${u-boot}\0"     \
 111                 "upd=run load; run prog\0"              \
 112                 "prog=prot off 0 2ffff;"        \
 113                 "era 0 2ffff;"                  \
 114                 "cp.b ${loadaddr} 0 ${filesize};"       \
 115                 "save\0"                                \
 116                 ""
 117 #endif
 118
 119 #define CONFIG_HOSTNAME         M5253DEMO
 120
 121 #define CFG_PROMPT              "=> "
 122 #define CFG_LONGHELP            /* undef to save memory */
 123
 124 #if defined(CONFIG_CMD_KGDB)
 125 #       define CFG_CBSIZE               1024    /* Console I/O Buffer Size */
 126 #else
 127 #       define CFG_CBSIZE               256     /* Console I/O Buffer Size */
 128 #endif
 129 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 130 #define CFG_MAXARGS             16      /* max number of command args */
 131 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 132
 133 #define CFG_LOAD_ADDR           0x00100000
 134
 135 #define CFG_MEMTEST_START       0x400
 136 #define CFG_MEMTEST_END         0x380000
 137
 138 #define CFG_HZ                  1000
 139
 140 #undef CFG_PLL_BYPASS           /* bypass PLL for test purpose */
 141 #define CFG_FAST_CLK
 142 #ifdef CFG_FAST_CLK
 143 #       define CFG_PLLCR        0x1243E054
 144 #       define CFG_CLK          140000000
 145 #else
 146 #       define CFG_PLLCR        0x135a4140
 147 #       define CFG_CLK          70000000
 148 #endif
 149
 150 /*
 151  * Low Level Configuration Settings
 152  * (address mappings, register initial values, etc.)
 153  * You should know what you are doing if you make changes here.
 154  */
 155
 156 #define CFG_MBAR                0x10000000      /* Register Base Addrs */
 157 #define CFG_MBAR2               0x80000000      /* Module Base Addrs 2 */
 158
 159 /*
 160  * Definitions for initial stack pointer and data area (in DPRAM)
 161  */
 162 #define CFG_INIT_RAM_ADDR       0x20000000
 163 #define CFG_INIT_RAM_END        0x10000 /* End of used area in internal SRAM */
 164 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 165 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 166 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 167
 168 /*
 169  * Start addresses for the final memory configuration
 170  * (Set up by the startup code)
 171  * Please note that CFG_SDRAM_BASE _must_ start at 0
 172  */
 173 #define CFG_SDRAM_BASE          0x00000000
 174 #define CFG_SDRAM_SIZE          16      /* SDRAM size in MB */
 175
 176 #ifdef CONFIG_MONITOR_IS_IN_RAM
 177 #       define CFG_MONITOR_BASE 0x20000
 178 #else
 179 #       define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
 180 #endif
 181
 182 #define CFG_MONITOR_LEN         0x40000
 183 #define CFG_MALLOC_LEN          (256 << 10)
 184 #define CFG_BOOTPARAMS_LEN      (64*1024)
 185
 186 /*
 187  * For booting Linux, the board info and command line data
 188  * have to be in the first 8 MB of memory, since this is
 189  * the maximum mapped by the Linux kernel during initialization ??
 190  */
 191 #define CFG_BOOTMAPSZ           (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
 192
 193 /* FLASH organization */
 194 #define CFG_FLASH_BASE          (CFG_CSAR0 << 16)
 195 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 196 #define CFG_MAX_FLASH_SECT      2048    /* max number of sectors on one chip */
 197 #define CFG_FLASH_ERASE_TOUT    1000
 198
 199 #define FLASH_SST6401B          0x200
 200 #define SST_ID_xF6401B          0x236D236D
 201
 202 #undef CFG_FLASH_CFI
 203 #ifdef CFG_FLASH_CFI
 204 /*
 205  * Unable to use CFI driver, due to incompatible sector erase command by SST.
 206  * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 207  * 0x30 is block erase in SST
 208  */
 209 #       define CFG_FLASH_CFI_DRIVER     1
 210 #       define CFG_FLASH_SIZE           0x800000
 211 #       define CFG_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 212 #       define CONFIG_FLASH_CFI_LEGACY
 213 #else
 214 #       define CFG_SST_SECT             2048
 215 #       define CFG_SST_SECTSZ           0x1000
 216 #       define CFG_FLASH_WRITE_TOUT     500
 217 #endif
 218
 219 /* Cache Configuration */
 220 #define CFG_CACHELINE_SIZE      16
 221
 222 /* Port configuration */
 223 #define CFG_FECI2C              0xF0
 224
 225 #define CFG_CSAR0               0xFF80
 226 #define CFG_CSMR0               0x007F0021
 227 #define CFG_CSCR0               0x1D80
 228
 229 #define CFG_CSAR1               0xE000
 230 #define CFG_CSMR1               0x00000001
 231 #define CFG_CSCR1               0x3DD8
 232
 233 #define CFG_CSAR2               0
 234 #define CFG_CSMR2               0
 235 #define CFG_CSCR2               0
 236
 237 #define CFG_CSAR3               0
 238 #define CFG_CSMR3               0
 239 #define CFG_CSCR3               0
 240
 241 /*-----------------------------------------------------------------------
 242  * Port configuration
 243  */
 244 #define CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none */
 245 #define CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54 */
 246 #define CFG_GPIO_EN             0x00000008      /* Set gpio output enable */
 247 #define CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable */
 248 #define CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
 249 #define CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
 250 #define CFG_GPIO1_LED           0x00400000      /* user led */
 251
 252 #endif                          /* _M5253DEMO_H */